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client-ip=165.204.84.17; helo=SATLEXMB04.amd.com; pr=C Received: from SATLEXMB04.amd.com (165.204.84.17) by DS3PEPF0000C37C.mail.protection.outlook.com (10.167.23.6) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.20.9031.11 via Frontend Transport; Tue, 12 Aug 2025 21:31:55 +0000 Received: from SCS-L-bcheatha.amd.com (10.180.168.240) by SATLEXMB04.amd.com (10.181.40.145) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.39; Tue, 12 Aug 2025 16:31:55 -0500 From: Ben Cheatham To: CC: Ben Cheatham Subject: [RFC PATCH 10/18] cxl/cache: Add cxl_cache driver Date: Tue, 12 Aug 2025 16:29:13 -0500 Message-ID: <20250812212921.9548-11-Benjamin.Cheatham@amd.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250812212921.9548-1-Benjamin.Cheatham@amd.com> References: <20250812212921.9548-1-Benjamin.Cheatham@amd.com> Precedence: bulk X-Mailing-List: linux-cxl@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-ClientProxiedBy: SATLEXMB04.amd.com (10.181.40.145) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: DS3PEPF0000C37C:EE_|IA1PR12MB6625:EE_ X-MS-Office365-Filtering-Correlation-Id: 9200ca03-2e40-45db-c78b-08ddd9e7a953 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|376014|36860700013|1800799024|82310400026; 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 12 Aug 2025 21:31:55.7187 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 9200ca03-2e40-45db-c78b-08ddd9e7a953 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: DS3PEPF0000C37C.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: IA1PR12MB6625 Add the cxl_cache driver which will manage struct cxl_cachdev devices. This driver will provide common management functions for some of a cache capable endpoint. This driver will also be responsible for validating the system's CXL.cache configuration. The driver expects the device's cache capabilities to be prefetched by the endpoint-specific driver. The required capabilities can be gotten by calling cxl_accel_get_cache_info(). Signed-off-by: Ben Cheatham --- drivers/cxl/Kconfig | 14 +++++ drivers/cxl/Makefile | 2 + drivers/cxl/cache.c | 116 +++++++++++++++++++++++++++++++++++++++++ drivers/cxl/cxlcache.h | 3 ++ 4 files changed, 135 insertions(+) create mode 100644 drivers/cxl/cache.c diff --git a/drivers/cxl/Kconfig b/drivers/cxl/Kconfig index 48b7314afdb8..6b07212b554a 100644 --- a/drivers/cxl/Kconfig +++ b/drivers/cxl/Kconfig @@ -233,4 +233,18 @@ config CXL_MCE def_bool y depends on X86_MCE && MEMORY_FAILURE +config CXL_CACHE + tristate "CXL: Cache Management Support" + depends on CXL_BUS + help + Enables a driver that manages the CXL.cache capabilities of a CXL.cache + capable CXL device. This driver validates and provides support for + programming the CXL cache device topology. This driver is required for + using multiple CXL.cache devices (Type 1 or Type 2) below a given + CXL 3.0+ capable PCIe Root Port. This driver only provides CXL cache + management and reporting capabilities, a vendor-specific device driver + is expected to enable the full capabilities of the device. + + If unsure, say 'm'. + endif diff --git a/drivers/cxl/Makefile b/drivers/cxl/Makefile index 2caa90fa4bf2..1017206d6780 100644 --- a/drivers/cxl/Makefile +++ b/drivers/cxl/Makefile @@ -13,9 +13,11 @@ obj-$(CONFIG_CXL_ACPI) += cxl_acpi.o obj-$(CONFIG_CXL_PMEM) += cxl_pmem.o obj-$(CONFIG_CXL_MEM) += cxl_mem.o obj-$(CONFIG_CXL_PCI) += cxl_pci.o +obj-$(CONFIG_CXL_CACHE) += cxl_cache.o cxl_port-y := port.o cxl_acpi-y := acpi.o cxl_pmem-y := pmem.o security.o cxl_mem-y := mem.o cxl_pci-y := pci.o +cxl_cache-y := cache.o diff --git a/drivers/cxl/cache.c b/drivers/cxl/cache.c new file mode 100644 index 000000000000..6e5161ae3107 --- /dev/null +++ b/drivers/cxl/cache.c @@ -0,0 +1,116 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* Copyright (C) 2025 Advanced Micro Devices, Inc. */ +#include "cxlcache.h" +#include "private.h" + +/** + * DOC: cxl cache + * + * The cxl_cache driver is responsible for validating the CXL.cache system + * configuration and managing portions of the CXL cache of CXL.cache enabled + * devices in the system. This driver does not discover devices, a + * device-specific driver is required for discovery and portions of set up. + */ + +/** + * devm_cxl_add_cachedev - Add a CXL cache device + * @host: devres alloc/release context and parent for the cachedev + * @cxlds: CXL device state to associate with the cachedev + * @ops: optional operations to run in cxl_cache::{probe,remove}() context + * + * Upon return the device will have had a chance to attach to the + * cxl_cache driver. This may fail if the CXL topology is not ready + * (hardware CXL link down, or software platform CXL root not attached) + * or the CXL.cache system configuration is invalid. + */ +struct cxl_cachedev *devm_cxl_add_cachedev(struct device *host, + struct cxl_dev_state *cxlds, + const struct cxl_dev_ops *ops) +{ + struct cxl_cachedev *cxlcd; + int rc; + + cxlcd = cxl_cachedev_alloc(cxlds, ops); + if (IS_ERR(cxlcd)) + return cxlcd; + + rc = dev_set_name(&cxlcd->dev, "cache%d", cxlcd->id); + if (rc) { + put_device(&cxlcd->dev); + return ERR_PTR(rc); + } + + cxlcd = devm_cxl_cachedev_add_or_reset(host, cxlcd); + if (IS_ERR(cxlcd)) + return cxlcd; + + guard(device)(&cxlcd->dev); + if (ops && !cxlcd->dev.driver) { + if (IS_ERR(cxlcd->endpoint)) + return ERR_CAST(cxlcd->endpoint); + return ERR_PTR(-ENXIO); + } + + return cxlcd; +} +EXPORT_SYMBOL_NS_GPL(devm_cxl_add_cachedev, "CXL"); + +static int cxl_cache_probe(struct device *dev) +{ + struct cxl_cachedev *cxlcd = to_cxl_cachedev(dev); + struct device *endpoint_parent; + struct cxl_dport *dport; + int rc; + + rc = devm_cxl_enumerate_ports(&cxlcd->dev); + if (rc) + return rc; + + struct cxl_port *parent_port __free(put_cxl_port) = + cxl_dev_find_port(&cxlcd->dev, &dport); + if (!parent_port) { + dev_err(dev, "CXL port topology not found\n"); + return -ENXIO; + } + + if (dport->rch) + endpoint_parent = parent_port->uport_dev; + else + endpoint_parent = &parent_port->dev; + + scoped_guard(device, endpoint_parent) { + if (!endpoint_parent->driver) { + dev_err(dev, "CXL port topology %s not enabled\n", + dev_name(endpoint_parent)); + return -ENXIO; + } + + rc = devm_cxl_add_endpoint(endpoint_parent, &cxlcd->dev, dport); + if (rc) + return rc; + } + + if (cxlcd->ops) { + rc = cxlcd->ops->probe(&cxlcd->dev); + if (rc) + return rc; + } + + return 0; +} + +static struct cxl_driver cxl_cache_driver = { + .name = "cxl_cache", + .probe = cxl_cache_probe, + .drv = { + .probe_type = PROBE_FORCE_SYNCHRONOUS, + }, + .id = CXL_DEVICE_ACCELERATOR, +}; + +module_cxl_driver(cxl_cache_driver); + +MODULE_DESCRIPTION("CXL: Cache Management"); +MODULE_LICENSE("GPL"); +MODULE_IMPORT_NS("CXL"); +MODULE_ALIAS_CXL(CXL_DEVICE_ACCELERATOR); diff --git a/drivers/cxl/cxlcache.h b/drivers/cxl/cxlcache.h index 3880312cd49d..a707e402b000 100644 --- a/drivers/cxl/cxlcache.h +++ b/drivers/cxl/cxlcache.h @@ -22,4 +22,7 @@ static inline struct cxl_cachedev *to_cxl_cachedev(struct device *dev) bool is_cxl_cachedev(const struct device *dev); int cxl_accel_get_cache_info(struct cxl_dev_state *cxlds); +struct cxl_cachedev *devm_cxl_add_cachedev(struct device *host, + struct cxl_dev_state *cxlds, + const struct cxl_dev_ops *ops); #endif -- 2.34.1