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client-ip=165.204.84.17; helo=SATLEXMB04.amd.com; pr=C Received: from SATLEXMB04.amd.com (165.204.84.17) by DS3PEPF0000C37D.mail.protection.outlook.com (10.167.23.7) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.20.9031.11 via Frontend Transport; Tue, 12 Aug 2025 21:32:11 +0000 Received: from SCS-L-bcheatha.amd.com (10.180.168.240) by SATLEXMB04.amd.com (10.181.40.145) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.39; Tue, 12 Aug 2025 16:32:11 -0500 From: Ben Cheatham To: CC: Ben Cheatham Subject: [RFC PATCH 11/18] cxl/core: Add CXL snoop filter setup and checking Date: Tue, 12 Aug 2025 16:29:14 -0500 Message-ID: <20250812212921.9548-12-Benjamin.Cheatham@amd.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250812212921.9548-1-Benjamin.Cheatham@amd.com> References: <20250812212921.9548-1-Benjamin.Cheatham@amd.com> Precedence: bulk X-Mailing-List: linux-cxl@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-ClientProxiedBy: SATLEXMB04.amd.com (10.181.40.145) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: DS3PEPF0000C37D:EE_|MW4PR12MB7333:EE_ X-MS-Office365-Filtering-Correlation-Id: 21ff939e-ae7b-4d99-94fe-08ddd9e7b2e1 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|82310400026|1800799024|36860700013|376014; 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 12 Aug 2025 21:32:11.7469 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 21ff939e-ae7b-4d99-94fe-08ddd9e7b2e1 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: DS3PEPF0000C37D.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: MW4PR12MB7333 Add functions to set up and validate the snoop filter configuration of a CXL-capable PCIe Root Port (struct cxl_dport). Allocate space in the snoop filter as part of cxl_cachedev probe. Signed-off-by: Ben Cheatham --- drivers/cxl/cache.c | 26 +++++++ drivers/cxl/core/port.c | 145 ++++++++++++++++++++++++++++++++++++++++ drivers/cxl/core/regs.c | 7 ++ drivers/cxl/cxl.h | 14 ++++ drivers/cxl/cxlcache.h | 3 + 5 files changed, 195 insertions(+) diff --git a/drivers/cxl/cache.c b/drivers/cxl/cache.c index 6e5161ae3107..7ef36e4bbce8 100644 --- a/drivers/cxl/cache.c +++ b/drivers/cxl/cache.c @@ -55,11 +55,29 @@ struct cxl_cachedev *devm_cxl_add_cachedev(struct device *host, } EXPORT_SYMBOL_NS_GPL(devm_cxl_add_cachedev, "CXL"); +static int find_snoop_gid(struct cxl_cachedev *cxlcd, u32 *gid) +{ + struct cxl_dport *iter = cxlcd->endpoint->parent_dport; + + while (iter && !is_cxl_root(iter->port)) { + if (iter->snoop_id != CXL_SNOOP_ID_NO_ID) { + *gid = iter->snoop_id; + return 0; + } + + iter = iter->port->parent_dport; + } + + *gid = CXL_SNOOP_ID_NO_ID; + return -ENXIO; +} + static int cxl_cache_probe(struct device *dev) { struct cxl_cachedev *cxlcd = to_cxl_cachedev(dev); struct device *endpoint_parent; struct cxl_dport *dport; + u32 gid; int rc; rc = devm_cxl_enumerate_ports(&cxlcd->dev); @@ -96,6 +114,14 @@ static int cxl_cache_probe(struct device *dev) return rc; } + rc = find_snoop_gid(cxlcd, &gid); + if (rc) + return rc; + + rc = devm_cxl_snoop_filter_alloc(gid, cxlcd->cxlds); + if (rc) + return rc; + return 0; } diff --git a/drivers/cxl/core/port.c b/drivers/cxl/core/port.c index 5144ddac7145..26ea22a2638c 100644 --- a/drivers/cxl/core/port.c +++ b/drivers/cxl/core/port.c @@ -35,6 +35,9 @@ static DEFINE_IDA(cxl_port_ida); static DEFINE_XARRAY(cxl_root_buses); static DEFINE_XARRAY(cxl_root_ports); +DECLARE_RWSEM(cxl_snoop_rwsem); +static DEFINE_XARRAY(cxl_snoop_filters); + /* * The terminal device in PCI is NULL and @platform_bus * for platform devices (for cxl_test) @@ -809,6 +812,139 @@ static int cxl_dport_setup_regs(struct device *host, struct cxl_dport *dport, return rc; } +struct cxl_snoop_filter { + u64 size; + struct xarray dports; + struct xarray devs; + struct mutex lock; /* Used for filter allocations */ +}; + +static struct cxl_snoop_filter *cxl_create_snoop_filter(struct cxl_dport *dport, + u32 gid, u32 size) +{ + struct cxl_snoop_filter *sf; + int rc; + + sf = xa_load(&cxl_snoop_filters, gid); + if (sf) + return sf; + + guard(rwsem_write)(&cxl_snoop_rwsem); + sf = kzalloc(sizeof(*sf), GFP_KERNEL); + if (!sf) + return ERR_PTR(-ENOMEM); + + sf->size = size; + xa_init(&sf->dports); + xa_init(&sf->devs); + mutex_init(&sf->lock); + + rc = xa_insert(&sf->dports, (unsigned long)dport->dport_dev, dport, + GFP_KERNEL); + if (rc) + goto err; + + rc = xa_insert(&cxl_snoop_filters, gid, sf, GFP_KERNEL); + if (rc) + goto err; + + return 0; + +err: + xa_destroy(&sf->dports); + xa_destroy(&sf->devs); + mutex_destroy(&sf->lock); + kfree(sf); + return ERR_PTR(rc); +} + +static void cxl_destroy_snoop_filters(void) +{ + struct cxl_snoop_filter *sf; + unsigned long gid; + + guard(rwsem_write)(&cxl_snoop_rwsem); + xa_for_each(&cxl_snoop_filters, gid, sf) { + xa_destroy(&sf->dports); + xa_destroy(&sf->devs); + mutex_destroy(&sf->lock); + } + + xa_destroy(&cxl_snoop_filters); +} + +static void cxl_snoop_filter_free(void *data) +{ + struct cxl_cache_state *cstate = data; + struct cxl_snoop_filter *sf; + + sf = xa_load(&cxl_snoop_filters, cstate->snoop_id); + if (!sf) + return; + + guard(mutex)(&sf->lock); + sf->size += cstate->size; +} + +int devm_cxl_snoop_filter_alloc(u32 gid, struct cxl_dev_state *cxlds) +{ + struct cxl_cache_state *cstate = &cxlds->cstate; + struct cxl_snoop_filter *sf; + + sf = xa_load(&cxl_snoop_filters, gid); + if (!sf) + return -ENODEV; + + guard(mutex)(&sf->lock); + if (cstate->size > sf->size) + return -EBUSY; + + sf->size -= cstate->size; + cstate->snoop_id = gid; + return devm_add_action_or_reset(cxlds->dev, cxl_snoop_filter_free, + cstate); +} +EXPORT_SYMBOL_NS_GPL(devm_cxl_snoop_filter_alloc, "CXL"); + +int cxl_dport_setup_snoop_filter(struct cxl_dport *dport) +{ + struct cxl_port *port = dport->port, *parent_port; + struct cxl_snoop_filter *sf; + u32 snoop, gid, size; + int rc; + + /* Only supported by CXL-enabled PCIe root ports */ + parent_port = parent_port_of(port); + if (!parent_port || !is_cxl_root(parent_port)) + return 0; + + if (!dport->reg_map.component_map.snoop.valid) { + dev_dbg(dport->dport_dev, "missing snoop filter capability\n"); + return -ENXIO; + } + + rc = cxl_map_component_regs(&dport->reg_map, &dport->regs.component, + BIT(CXL_CM_CAP_CAP_ID_SNOOP)); + if (rc) + return rc; + + snoop = readl(dport->regs.snoop + CXL_SNOOP_GROUP_ID_OFFSET); + gid = FIELD_GET(CXL_SNOOP_GROUP_ID_MASK, snoop); + + snoop = readl(dport->regs.snoop + CXL_SNOOP_FILTER_SIZE_OFFSET); + size = FIELD_GET(CXL_SNOOP_FILTER_SIZE_MASK, snoop); + if (!size) + return -ENXIO; + + sf = cxl_create_snoop_filter(dport, gid, size); + if (IS_ERR(sf)) + return PTR_ERR(sf); + + dport->snoop_id = gid; + return 0; +} +EXPORT_SYMBOL_NS_GPL(cxl_dport_setup_snoop_filter, "CXL"); + DEFINE_SHOW_ATTRIBUTE(einj_cxl_available_error_type); static int cxl_einj_inject(void *data, u64 type) @@ -1202,6 +1338,7 @@ __devm_cxl_add_dport(struct cxl_port *port, struct device *dport_dev, dport->dport_dev = dport_dev; dport->port_id = port_id; dport->port = port; + dport->snoop_id = CXL_SNOOP_ID_NO_ID; if (rcrb == CXL_RESOURCE_NONE) { rc = cxl_dport_setup_regs(&port->dev, dport, @@ -1686,10 +1823,17 @@ static int update_decoders_with_dport(struct cxl_port *port, struct cxl_dport *d static int cxl_port_setup_with_dport(struct cxl_port *port, struct cxl_dport *dport) { + int rc; + device_lock_assert(&port->dev); cxl_switch_parse_cdat(dport); + rc = cxl_dport_setup_snoop_filter(dport); + if (rc) + dev_dbg(dport->dport_dev, + "failed to set up snoop filter capability: %d\n", rc); + return update_decoders_with_dport(port, dport); } @@ -2711,6 +2855,7 @@ static void cxl_core_exit(void) bus_unregister(&cxl_bus_type); destroy_workqueue(cxl_bus_wq); cxl_memdev_exit(); + cxl_destroy_snoop_filters(); debugfs_remove_recursive(cxl_debugfs); } diff --git a/drivers/cxl/core/regs.c b/drivers/cxl/core/regs.c index 5ca7b0eed568..0c8962fcad9b 100644 --- a/drivers/cxl/core/regs.c +++ b/drivers/cxl/core/regs.c @@ -92,6 +92,12 @@ void cxl_probe_component_regs(struct device *dev, void __iomem *base, length = CXL_RAS_CAPABILITY_LENGTH; rmap = &map->ras; break; + case CXL_CM_CAP_CAP_ID_SNOOP: + dev_dbg(dev, "found Snoop filter capability (0x%x)\n", + offset); + length = CXL_SNOOP_FILTER_CAPABILITY_LENGTH; + rmap = &map->snoop; + break; default: dev_dbg(dev, "Unknown CM cap ID: %d (0x%x)\n", cap_id, offset); @@ -211,6 +217,7 @@ int cxl_map_component_regs(const struct cxl_register_map *map, } mapinfo[] = { { &map->component_map.hdm_decoder, ®s->hdm_decoder }, { &map->component_map.ras, ®s->ras }, + { &map->component_map.snoop, ®s->snoop }, }; int i; diff --git a/drivers/cxl/cxl.h b/drivers/cxl/cxl.h index 1771c42a1e3b..2881e0826829 100644 --- a/drivers/cxl/cxl.h +++ b/drivers/cxl/cxl.h @@ -40,6 +40,7 @@ extern const struct nvdimm_security_ops *cxl_security_ops; #define CXL_CM_CAP_CAP_ID_RAS 0x2 #define CXL_CM_CAP_CAP_ID_HDM 0x5 +#define CXL_CM_CAP_CAP_ID_SNOOP 0x9 #define CXL_CM_CAP_CAP_HDM_VERSION 1 /* HDM decoders CXL 2.0 8.2.5.12 CXL HDM Decoder Capability Structure */ @@ -151,6 +152,13 @@ static inline int ways_to_eiw(unsigned int ways, u8 *eiw) #define CXL_HEADERLOG_SIZE SZ_512 #define CXL_HEADERLOG_SIZE_U32 SZ_512 / sizeof(u32) +/* CXL 3.2 8.2.4.23 CXL Snoop Filter Capability Structure */ +#define CXL_SNOOP_GROUP_ID_OFFSET 0x0 +#define CXL_SNOOP_GROUP_ID_MASK GENMASK(15, 0) +#define CXL_SNOOP_FILTER_SIZE_OFFSET 0x4 +#define CXL_SNOOP_FILTER_SIZE_MASK GENMASK(31, 0) +#define CXL_SNOOP_FILTER_CAPABILITY_LENGTH 0x8 + /* CXL 2.0 8.2.8.1 Device Capabilities Array Register */ #define CXLDEV_CAP_ARRAY_OFFSET 0x0 #define CXLDEV_CAP_ARRAY_CAP_ID 0 @@ -214,6 +222,7 @@ struct cxl_regs { struct_group_tagged(cxl_component_regs, component, void __iomem *hdm_decoder; void __iomem *ras; + void __iomem *snoop; ); /* * Common set of CXL Device register block base pointers @@ -256,6 +265,7 @@ struct cxl_reg_map { struct cxl_component_reg_map { struct cxl_reg_map hdm_decoder; struct cxl_reg_map ras; + struct cxl_reg_map snoop; }; struct cxl_device_reg_map { @@ -658,6 +668,8 @@ struct cxl_rcrb_info { u16 aer_cap; }; +#define CXL_SNOOP_ID_NO_ID (-1) + /** * struct cxl_dport - CXL downstream port * @dport_dev: PCI bridge or firmware device representing the downstream link @@ -682,6 +694,7 @@ struct cxl_dport { struct access_coordinate coord[ACCESS_COORDINATE_MAX]; long link_latency; int gpf_dvsec; + int snoop_id; }; /** @@ -756,6 +769,7 @@ struct cxl_dev_ops { struct cxl_cache_state { u64 size; u32 unit; + u16 snoop_id; }; /** diff --git a/drivers/cxl/cxlcache.h b/drivers/cxl/cxlcache.h index a707e402b000..c4862f7e6edc 100644 --- a/drivers/cxl/cxlcache.h +++ b/drivers/cxl/cxlcache.h @@ -25,4 +25,7 @@ int cxl_accel_get_cache_info(struct cxl_dev_state *cxlds); struct cxl_cachedev *devm_cxl_add_cachedev(struct device *host, struct cxl_dev_state *cxlds, const struct cxl_dev_ops *ops); + +int cxl_dport_setup_snoop_filter(struct cxl_dport *dport); +int devm_cxl_snoop_filter_alloc(u32 gid, struct cxl_dev_state *cxlds); #endif -- 2.34.1