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client-ip=165.204.84.17; helo=SATLEXMB04.amd.com; pr=C Received: from SATLEXMB04.amd.com (165.204.84.17) by DS3PEPF0000C381.mail.protection.outlook.com (10.167.23.11) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.20.9031.11 via Frontend Transport; Tue, 12 Aug 2025 21:32:39 +0000 Received: from SCS-L-bcheatha.amd.com (10.180.168.240) by SATLEXMB04.amd.com (10.181.40.145) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.39; Tue, 12 Aug 2025 16:32:38 -0500 From: Ben Cheatham To: CC: Ben Cheatham Subject: [RFC PATCH 13/18] cxl/cache: Implement Cache ID Route Table programming Date: Tue, 12 Aug 2025 16:29:16 -0500 Message-ID: <20250812212921.9548-14-Benjamin.Cheatham@amd.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250812212921.9548-1-Benjamin.Cheatham@amd.com> References: <20250812212921.9548-1-Benjamin.Cheatham@amd.com> Precedence: bulk X-Mailing-List: linux-cxl@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-ClientProxiedBy: SATLEXMB04.amd.com (10.181.40.145) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: DS3PEPF0000C381:EE_|LV3PR12MB9215:EE_ X-MS-Office365-Filtering-Correlation-Id: 136c394f-b265-403a-ca6f-08ddd9e7c35d X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|376014|36860700013|82310400026|1800799024; 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 12 Aug 2025 21:32:39.4032 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 136c394f-b265-403a-ca6f-08ddd9e7c35d X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: DS3PEPF0000C381.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: LV3PR12MB9215 The CXL Cache ID Route Table is an optional capability for CXL-enabled upstream switch ports and CXL host bridges. This capability is required for having multiple CXL.cache enabled devices under a single port (CXL 3.2 8.2.4.28). Implement route table programming. In the case BIOS has already programmed the route table(s), check the configuration for validity. Signed-off-by: Ben Cheatham --- drivers/cxl/cache.c | 4 ++ drivers/cxl/core/port.c | 135 ++++++++++++++++++++++++++++++++++++++++ drivers/cxl/cxl.h | 10 +++ drivers/cxl/cxlcache.h | 4 ++ 4 files changed, 153 insertions(+) diff --git a/drivers/cxl/cache.c b/drivers/cxl/cache.c index fd2ae1fa44bc..24559b9ba8e8 100644 --- a/drivers/cxl/cache.c +++ b/drivers/cxl/cache.c @@ -134,6 +134,10 @@ static int devm_cxl_cachedev_allocate_cache_id(struct cxl_cachedev *cxlcd) if (rc) return rc; } + + rc = devm_cxl_port_program_cache_idrt(port, dport, cxlcd); + if (rc) + return rc; } return 0; diff --git a/drivers/cxl/core/port.c b/drivers/cxl/core/port.c index 26ea22a2638c..f491796f6e60 100644 --- a/drivers/cxl/core/port.c +++ b/drivers/cxl/core/port.c @@ -945,6 +945,141 @@ int cxl_dport_setup_snoop_filter(struct cxl_dport *dport) } EXPORT_SYMBOL_NS_GPL(cxl_dport_setup_snoop_filter, "CXL"); +static int cxl_port_commit_idrt(struct cxl_port *port) +{ + unsigned long timeout, start, end; + u32 cap, ctrl, status; + int i; + + cap = readl(port->regs.cidrt + CXL_CACHE_IDRT_CAP_OFFSET); + if (!(cap & CXL_CACHE_IDRT_CAP_COMMIT)) + return 0; + + ctrl = readl(port->regs.cidrt + CXL_CACHE_IDRT_CTRL_OFFSET); + if (ctrl & CXL_CACHE_IDRT_CTRL_COMMIT) { + ctrl &= ~CXL_CACHE_IDRT_CTRL_COMMIT; + writel(ctrl, port->regs.cidrt + CXL_CACHE_IDRT_CTRL_OFFSET); + } + + ctrl |= CXL_CACHE_IDRT_CTRL_COMMIT; + writel(ctrl, port->regs.cidrt + CXL_CACHE_IDRT_CTRL_OFFSET); + + status = readl(port->regs.cidrt + CXL_CACHE_IDRT_STAT_OFFSET); + + i = FIELD_GET(CXL_CACHE_IDRT_STAT_TIMEOUT_SCALE_MASK, status); + timeout = 1 * HZ; + while (i-- > 3) + timeout *= 10; + + timeout *= FIELD_GET(CXL_CACHE_IDRT_STAT_TIMEOUT_BASE_MASK, status); + start = jiffies; + do { + status = readl(port->regs.cidrt + CXL_CACHE_IDRT_STAT_OFFSET); + if (status & CXL_CACHE_IDRT_STAT_ERR_COMMIT) + return -EBUSY; + + if (status & CXL_CACHE_IDRT_STAT_COMMITTED) + return 0; + + end = jiffies; + } while (time_before(end, start + timeout)); + + return -ETIMEDOUT; +} + +struct cxl_cache_idrt_entry { + struct cxl_port *port; + int port_num; + int id; +}; + +static int cxl_port_enable_idrt_entry(struct cxl_cache_idrt_entry *entry) +{ + struct cxl_port *port = entry->port; + int id = entry->id, port_num; + u32 entry_n; + + entry_n = readl(port->regs.cidrt + CXL_CACHE_IDRT_TARGETN_OFFSET(id)); + if (entry_n & CXL_CACHE_IDRT_TARGETN_VALID) { + port_num = FIELD_GET(CXL_CACHE_IDRT_TARGETN_PORT_MASK, entry_n); + if (port_num != entry->port_num) { + dev_err(&port->dev, + "Cache ID Route Table entry%d: Invalid port id %d, expected %d\n", + id, port_num, entry->port_num); + return -EINVAL; + } + + return 0; + } + + entry_n &= ~CXL_CACHE_IDRT_TARGETN_PORT_MASK; + entry_n |= FIELD_PREP(CXL_CACHE_IDRT_TARGETN_PORT_MASK, entry->port_num); + entry_n |= CXL_CACHE_IDRT_TARGETN_VALID; + writel(entry_n, port->regs.cidrt + CXL_CACHE_IDRT_TARGETN_OFFSET(id)); + + return cxl_port_commit_idrt(port); +} + +static void free_cache_idrt_entry(void *data) +{ + struct cxl_cache_idrt_entry *entry = data; + struct cxl_port *port = entry->port; + int id = entry->id; + u32 cap, entry_n; + + cap = readl(port->regs.cidrt + CXL_CACHE_IDRT_CAP_OFFSET); + if (FIELD_GET(CXL_CACHE_IDRT_CAP_CNT_MASK, cap) < id) + return; + + entry_n = readl(port->regs.cidrt + CXL_CACHE_IDRT_TARGETN_OFFSET(id)); + entry_n &= ~CXL_CACHE_IDRT_TARGETN_VALID; + writel(entry_n, port->regs.cidrt + CXL_CACHE_IDRT_TARGETN_OFFSET(id)); + + cxl_port_commit_idrt(port); + + kfree(entry); +} + +int devm_cxl_port_program_cache_idrt(struct cxl_port *port, + struct cxl_dport *dport, + struct cxl_cachedev *cxlcd) +{ + struct cxl_cache_state *cstate = &cxlcd->cxlds->cstate; + int id = cstate->cache_id, rc; + u32 cap, max_hdmd; + + cap = readl(port->regs.cidrt + CXL_CACHE_IDRT_CAP_OFFSET); + if (FIELD_GET(CXL_CACHE_IDRT_CAP_CNT_MASK, cap) < id) + return -EINVAL; + + if (is_cxl_root(parent_port_of(port))) { + max_hdmd = FIELD_GET(CXL_CACHE_IDRT_CAP_T2_MAX_MASK, cap); + if (cxlcd->cxlds->type == CXL_DEVTYPE_DEVMEM && cstate->hdmd) + port->nr_hdmd++; + + if (port->nr_hdmd > max_hdmd) { + port->nr_hdmd--; + return -EINVAL; + } + } + + struct cxl_cache_idrt_entry *entry __free(kfree) = + kzalloc(sizeof(*entry), GFP_KERNEL); + if (!entry) + return -ENXIO; + + entry->port_num = dport->port_id; + entry->port = port; + entry->id = id; + + rc = cxl_port_enable_idrt_entry(entry); + if (rc) + return rc; + + return devm_add_action(&cxlcd->dev, free_cache_idrt_entry, entry); +} +EXPORT_SYMBOL_NS_GPL(devm_cxl_port_program_cache_idrt, "CXL"); + DEFINE_SHOW_ATTRIBUTE(einj_cxl_available_error_type); static int cxl_einj_inject(void *data, u64 type) diff --git a/drivers/cxl/cxl.h b/drivers/cxl/cxl.h index c147846855e2..1a2918aaee62 100644 --- a/drivers/cxl/cxl.h +++ b/drivers/cxl/cxl.h @@ -163,8 +163,15 @@ static inline int ways_to_eiw(unsigned int ways, u8 *eiw) /* CXL 3.2 8.2.4.28 CXL Cache ID Route Table Capability Structure */ #define CXL_CACHE_IDRT_CAP_OFFSET 0x0 #define CXL_CACHE_IDRT_CAP_CNT_MASK GENMASK(4, 0) +#define CXL_CACHE_IDRT_CAP_T2_MAX_MASK GENMASK(11, 8) +#define CXL_CACHE_IDRT_CAP_COMMIT BIT(16) +#define CXL_CACHE_IDRT_CTRL_OFFSET 0x4 +#define CXL_CACHE_IDRT_CTRL_COMMIT BIT(0) #define CXL_CACHE_IDRT_STAT_OFFSET 0x8 #define CXL_CACHE_IDRT_STAT_COMMITTED BIT(0) +#define CXL_CACHE_IDRT_STAT_ERR_COMMIT BIT(0) +#define CXL_CACHE_IDRT_STAT_TIMEOUT_SCALE_MASK GENMASK(11, 8) +#define CXL_CACHE_IDRT_STAT_TIMEOUT_BASE_MASK GENMASK(15, 12) #define CXL_CACHE_IDRT_TARGETN_OFFSET(n) (0x10 + (2 * (n))) #define CXL_CACHE_IDRT_TARGETN_VALID BIT(0) #define CXL_CACHE_IDRT_TARGETN_PORT_MASK GENMASK(15, 8) @@ -618,6 +625,7 @@ struct cxl_dax_region { * @cdat: Cached CDAT data * @cdat_available: Should a CDAT attribute be available in sysfs * @pci_latency: Upstream latency in picoseconds + * @nr_hdmd: Number of HDM-D devices below port */ struct cxl_port { struct device dev; @@ -643,6 +651,7 @@ struct cxl_port { } cdat; bool cdat_available; long pci_latency; + int nr_hdmd; }; /** @@ -786,6 +795,7 @@ struct cxl_cache_state { u32 unit; u16 snoop_id; int cache_id; + bool hdmd; }; /** diff --git a/drivers/cxl/cxlcache.h b/drivers/cxl/cxlcache.h index c4862f7e6edc..d28222123102 100644 --- a/drivers/cxl/cxlcache.h +++ b/drivers/cxl/cxlcache.h @@ -28,4 +28,8 @@ struct cxl_cachedev *devm_cxl_add_cachedev(struct device *host, int cxl_dport_setup_snoop_filter(struct cxl_dport *dport); int devm_cxl_snoop_filter_alloc(u32 gid, struct cxl_dev_state *cxlds); + +int devm_cxl_port_program_cache_idrt(struct cxl_port *port, + struct cxl_dport *dport, + struct cxl_cachedev *cxlcd); #endif -- 2.34.1