Re: [PATCH 02/13] spi: spi-fsl-lpspi: Set correct chip-select polarity bit

[kernel test robot <lkp@intel.com>]

Hi James,

kernel test robot noticed the following build errors:

[auto build test ERROR on 0cc53520e68bea7fb80fdc6bdf8d226d1b6a98d9]

url:    https://github.com/intel-lab-lkp/linux/commits/James-Clark/spi-spi-fsl-lpspi-Fix-transmissions-when-using-CONT/20250815-001554
base:   0cc53520e68bea7fb80fdc6bdf8d226d1b6a98d9
patch link:    https://lore.kernel.org/r/20250814-james-nxp-lpspi-v1-2-9586d7815d14%40linaro.org
patch subject: [PATCH 02/13] spi: spi-fsl-lpspi: Set correct chip-select polarity bit
config: csky-randconfig-002-20250815 (https://download.01.org/0day-ci/archive/20250815/202508151101.7lDGTaxi-lkp@intel.com/config)
compiler: csky-linux-gcc (GCC) 15.1.0
reproduce (this is a W=1 build): (https://download.01.org/0day-ci/archive/20250815/202508151101.7lDGTaxi-lkp@intel.com/reproduce)

If you fix the issue in a separate patch/commit (i.e. not just a new version of
the same patch/commit), kindly add following tags
| Reported-by: kernel test robot <lkp@intel.com>
| Closes: https://lore.kernel.org/oe-kbuild-all/202508151101.7lDGTaxi-lkp@intel.com/

All errors (new ones prefixed by >>):

   drivers/spi/spi-fsl-lpspi.c: In function 'fsl_lpspi_config':
>> drivers/spi/spi-fsl-lpspi.c:428:25: error: implicit declaration of function 'FIELD_PREP' [-Wimplicit-function-declaration]
     428 |                 temp |= FIELD_PREP(CFGR1_PCSPOL_MASK,
         |                         ^~~~~~~~~~


vim +/FIELD_PREP +428 drivers/spi/spi-fsl-lpspi.c

   409	
   410	static int fsl_lpspi_config(struct fsl_lpspi_data *fsl_lpspi)
   411	{
   412		u32 temp;
   413		int ret;
   414	
   415		if (!fsl_lpspi->is_target) {
   416			ret = fsl_lpspi_set_bitrate(fsl_lpspi);
   417			if (ret)
   418				return ret;
   419		}
   420	
   421		fsl_lpspi_set_watermark(fsl_lpspi);
   422	
   423		if (!fsl_lpspi->is_target)
   424			temp = CFGR1_HOST;
   425		else
   426			temp = CFGR1_PINCFG;
   427		if (fsl_lpspi->config.mode & SPI_CS_HIGH)
 > 428			temp |= FIELD_PREP(CFGR1_PCSPOL_MASK,
   429					   BIT(fsl_lpspi->config.chip_select));
   430	
   431		writel(temp, fsl_lpspi->base + IMX7ULP_CFGR1);
   432	
   433		temp = readl(fsl_lpspi->base + IMX7ULP_CR);
   434		temp |= CR_RRF | CR_RTF | CR_MEN;
   435		writel(temp, fsl_lpspi->base + IMX7ULP_CR);
   436	
   437		temp = 0;
   438		if (fsl_lpspi->usedma)
   439			temp = DER_TDDE | DER_RDDE;
   440		writel(temp, fsl_lpspi->base + IMX7ULP_DER);
   441	
   442		return 0;
   443	}
   444	

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