From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 9619618A6DB; Sun, 17 Aug 2025 20:22:05 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1755462125; cv=none; b=LSIm3jl/8x0GlIzc1tn1hcyGcpCXwzPakImOmcOGioMscP4KXAD/QjwYAJ0tvQgbN+7K5jwC4ANb34584MgW4+QPLCvHztXyYYttO66GNRL3FlQ2K9j7wa4B1LpJNbIwMUbpGk597Ru0+6F64rJUiEhnX75SZ5QYXf1S4ik13+o= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1755462125; c=relaxed/simple; bh=RXgWRSGH4nGx0A8lxjTwK5dMqds4qncvFuceBa86+kY=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=TrS2iKmPqpIC/d761TupeYfWafWpA9+mG/AKqPkkC1cfOVoFbW6g3edZhNu+JegdoBoP1bFL8rMulLRdrO8NwlNtvhSeJ9hH1Cg8OA6tlv9sNXF5Wwn6nUcWBkfVKX0vSfiNlnLoDpHWe+FFQpQY6HcyLK+yuXbD+Iyta6u84FA= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=qsj6nrTU; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="qsj6nrTU" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 39544C4CEED; Sun, 17 Aug 2025 20:22:05 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1755462125; bh=RXgWRSGH4nGx0A8lxjTwK5dMqds4qncvFuceBa86+kY=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=qsj6nrTUnvYJ7KlkpI4Viy+RR1VJWN0kRVZ8DarcSE/KiLsCBVU7tG7V9Uo2vflx4 FYLyQ/vTqqsCZ+1K89hATqkTPCyHRWOGSzYKpnBNL7YJy2YYrTlWyhd+lbgZnPvB2o H8aQVQFSvvpY+B9nM9lbYttLMGFLLge0m1r8kYQLvYOPVXBmiytsURANAHQ8ohwoMd 296rQqmV5O9vU2q5LN3rKrWt/eN8mGYNVtIqv8CBF2DRyJh9CpAu5OTFhVZbcI/sfM QbQ2qptiGxtwCuM2ONUWbC1k4VddZhrZG/mgVjXygHCj5jm2baziP9Nljz2Owb4FYO Be3fLpOusr/Ww== Received: from sofa.misterjones.org ([185.219.108.64] helo=valley-girl.lan) by disco-boy.misterjones.org with esmtpsa (TLS1.3) tls TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384 (Exim 4.95) (envelope-from ) id 1unjtD-008PX0-1U; Sun, 17 Aug 2025 21:22:03 +0100 From: Marc Zyngier To: kvmarm@lists.linux.dev, linux-arm-kernel@lists.infradead.org, kvm@vger.kernel.org Cc: Joey Gouly , Suzuki K Poulose , Oliver Upton , Zenghui Yu , Will Deacon , Catalin Marinas , Cornelia Huck Subject: [PATCH v3 1/6] arm64: Add capability denoting FEAT_RASv1p1 Date: Sun, 17 Aug 2025 21:21:53 +0100 Message-Id: <20250817202158.395078-2-maz@kernel.org> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20250817202158.395078-1-maz@kernel.org> References: <20250817202158.395078-1-maz@kernel.org> Precedence: bulk X-Mailing-List: kvm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-SA-Exim-Connect-IP: 185.219.108.64 X-SA-Exim-Rcpt-To: kvmarm@lists.linux.dev, linux-arm-kernel@lists.infradead.org, kvm@vger.kernel.org, joey.gouly@arm.com, suzuki.poulose@arm.com, oliver.upton@linux.dev, yuzenghui@huawei.com, will@kernel.org, catalin.marinas@arm.com, cohuck@redhat.com X-SA-Exim-Mail-From: maz@kernel.org X-SA-Exim-Scanned: No (on disco-boy.misterjones.org); SAEximRunCond expanded to false Detecting FEAT_RASv1p1 is rather complicated, as there are two ways for the architecture to advertise the same thing (always a delight...). Add a capability that will advertise this in a synthetic way to the rest of the kernel. Acked-by: Catalin Marinas Signed-off-by: Marc Zyngier --- arch/arm64/kernel/cpufeature.c | 24 ++++++++++++++++++++++++ arch/arm64/tools/cpucaps | 1 + 2 files changed, 25 insertions(+) diff --git a/arch/arm64/kernel/cpufeature.c b/arch/arm64/kernel/cpufeature.c index 9ad065f15f1d6..0d45c5e9b4da5 100644 --- a/arch/arm64/kernel/cpufeature.c +++ b/arch/arm64/kernel/cpufeature.c @@ -2269,6 +2269,24 @@ static void cpu_clear_disr(const struct arm64_cpu_capabilities *__unused) /* Firmware may have left a deferred SError in this register. */ write_sysreg_s(0, SYS_DISR_EL1); } +static bool has_rasv1p1(const struct arm64_cpu_capabilities *__unused, int scope) +{ + const struct arm64_cpu_capabilities rasv1p1_caps[] = { + { + ARM64_CPUID_FIELDS(ID_AA64PFR0_EL1, RAS, V1P1) + }, + { + ARM64_CPUID_FIELDS(ID_AA64PFR0_EL1, RAS, IMP) + }, + { + ARM64_CPUID_FIELDS(ID_AA64PFR1_EL1, RAS_frac, RASv1p1) + }, + }; + + return (has_cpuid_feature(&rasv1p1_caps[0], scope) || + (has_cpuid_feature(&rasv1p1_caps[1], scope) && + has_cpuid_feature(&rasv1p1_caps[2], scope))); +} #endif /* CONFIG_ARM64_RAS_EXTN */ #ifdef CONFIG_ARM64_PTR_AUTH @@ -2687,6 +2705,12 @@ static const struct arm64_cpu_capabilities arm64_features[] = { .cpu_enable = cpu_clear_disr, ARM64_CPUID_FIELDS(ID_AA64PFR0_EL1, RAS, IMP) }, + { + .desc = "RASv1p1 Extension Support", + .capability = ARM64_HAS_RASV1P1_EXTN, + .type = ARM64_CPUCAP_SYSTEM_FEATURE, + .matches = has_rasv1p1, + }, #endif /* CONFIG_ARM64_RAS_EXTN */ #ifdef CONFIG_ARM64_AMU_EXTN { diff --git a/arch/arm64/tools/cpucaps b/arch/arm64/tools/cpucaps index ef0b7946f5a48..9ff5cdbd27597 100644 --- a/arch/arm64/tools/cpucaps +++ b/arch/arm64/tools/cpucaps @@ -53,6 +53,7 @@ HAS_S1PIE HAS_S1POE HAS_SCTLR2 HAS_RAS_EXTN +HAS_RASV1P1_EXTN HAS_RNG HAS_SB HAS_STAGE2_FWB -- 2.39.2