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[82.69.66.36]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-45b4e8de85bsm10376175e9.7.2025.08.21.05.28.08 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 21 Aug 2025 05:28:08 -0700 (PDT) Date: Thu, 21 Aug 2025 13:28:07 +0100 From: David Laight To: Peter Zijlstra Cc: Marcos Del Sol Vives , linux-kernel@vger.kernel.org, Thomas Gleixner , Ingo Molnar , Borislav Petkov , Dave Hansen , x86@kernel.org, "H. Peter Anvin" , Brian Gerst , Uros Bizjak , Ard Biesheuvel , David Kaplan , "Ahmed S. Darwish" , Kees Cook , Andrew Cooper , Oleg Nesterov , "Xin Li (Intel)" , Sabyrzhan Tasbolatov Subject: Re: [PATCH] x86: add hintable NOPs emulation Message-ID: <20250821132807.0a898dfa@pumpkin> In-Reply-To: <20250820090733.GJ3245006@noisy.programming.kicks-ass.net> References: <20250820013452.495481-1-marcos@orca.pet> <20250820090733.GJ3245006@noisy.programming.kicks-ass.net> X-Mailer: Claws Mail 4.1.1 (GTK 3.24.38; arm-unknown-linux-gnueabihf) Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=US-ASCII Content-Transfer-Encoding: 7bit On Wed, 20 Aug 2025 11:07:33 +0200 Peter Zijlstra wrote: > On Wed, Aug 20, 2025 at 03:34:46AM +0200, Marcos Del Sol Vives wrote: > > Hintable NOPs are a series of instructions introduced by Intel with the > > Pentium Pro (i686), and described in US patent US5701442A. > > > > These instructions were reserved to allow backwards-compatible changes > > in the instruction set possible, by having old processors treat them as > > variable-length NOPs, while having other semantics in modern processors. > > > > Some modern uses are: > > - Multi-byte/long NOPs > > - Indirect Branch Tracking (ENDBR32) > > - Shadow Stack (part of CET) > > > > Some processors advertising i686 compatibility lack full support for > > them, which may cause #UD to be incorrectly triggered, crashing software > > that uses then with an unexpected SIGILL. > > > > One such software is sudo in Debian bookworm, which is compiled with > > GCC -fcf-protection=branch and contains ENDBR32 instructions. It crashes > > on my Vortex86DX3 processor and VIA C3 Nehalem processors [1]. > > > > This patch is a much simplified version of my previous patch for x86 > > instruction emulation [2], that only emulates hintable NOPs. > > > > When #UD is raised, it checks if the opcode corresponds to a hintable NOP > > in user space. If true, it warns the user via the dmesg and advances the > > instruction pointer, thus emulating its expected NOP behaviour. > > > > [1]: https://lists.debian.org/debian-devel/2023/10/msg00118.html > > [2]: https://lore.kernel.org/all/20210626130313.1283485-1-marcos@orca.pet/ > > > > Signed-off-by: Marcos Del Sol Vives > > This is going to be terribly slow if there's a significant number of > traps (like with endbr32), but yeah, this ought to work. Could you patch the memory resident page to contain a supported nop? (without marking it 'dirty') Then the same function wouldn't trap until the code page was reloaded from the source file. David