Re: [PATCH 2/4] dt-bindings: Add bank width to Intel IXP4xx memory controller

[Rob Herring <robh@kernel.org>]

On Wed, Aug 20, 2025 at 12:59:44PM +0200, Linus Walleij wrote:
> This bank width is necessary to set up the memory controller
> properly unless the peripheral is using native bank width.

What's the native width?

> 
> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
> ---
>  .../memory-controllers/intel,ixp4xx-expansion-peripheral-props.yaml  | 5 +++++
>  1 file changed, 5 insertions(+)
> 
> diff --git a/Documentation/devicetree/bindings/memory-controllers/intel,ixp4xx-expansion-peripheral-props.yaml b/Documentation/devicetree/bindings/memory-controllers/intel,ixp4xx-expansion-peripheral-props.yaml
> index d1479a7b9c8df4dbefc24a4706b1fecdda37bc6a..e306344373c5cd5c1bc6f4001d1252d8d0485f60 100644
> --- a/Documentation/devicetree/bindings/memory-controllers/intel,ixp4xx-expansion-peripheral-props.yaml
> +++ b/Documentation/devicetree/bindings/memory-controllers/intel,ixp4xx-expansion-peripheral-props.yaml
> @@ -15,6 +15,11 @@ maintainers:
>    - Linus Walleij <linus.walleij@linaro.org>
>  
>  properties:
> +  bank-width:
> +    description: Width (in bytes) of the device on the chip select bank.
> +    $ref: /schemas/types.yaml#/definitions/uint32
> +    enum: [ 1, 2, 4 ]
> +

Is there a default? If so, we should be able to omit that width.

>    intel,ixp4xx-eb-t1:
>      description: Address timing, extend address phase with n cycles.
>      $ref: /schemas/types.yaml#/definitions/uint32
> 
> -- 
> 2.50.1
>