From: Jason Gunthorpe <jgg@nvidia.com>
To: "Tian, Kevin" <kevin.tian@intel.com>
Cc: Lu Baolu <baolu.lu@linux.intel.com>,
David Woodhouse <dwmw2@infradead.org>,
"iommu@lists.linux.dev" <iommu@lists.linux.dev>,
Joerg Roedel <joro@8bytes.org>,
Robin Murphy <robin.murphy@arm.com>,
Will Deacon <will@kernel.org>,
"patches@lists.linux.dev" <patches@lists.linux.dev>,
Tina Zhang <tina.zhang@intel.com>,
"Wang, Wei W" <wei.w.wang@intel.com>
Subject: Re: [PATCH 1/9] iommu/pages: Add support for a incoherent IOMMU page walker
Date: Fri, 22 Aug 2025 18:13:17 -0300 [thread overview]
Message-ID: <20250822211317.GE1405994@nvidia.com> (raw)
In-Reply-To: <BN9PR11MB5276865229DD850CFA873B448C34A@BN9PR11MB5276.namprd11.prod.outlook.com>
On Fri, Aug 15, 2025 at 11:28:06AM +0000, Tian, Kevin wrote:
> > From: Jason Gunthorpe <jgg@nvidia.com>
> > Sent: Thursday, July 17, 2025 3:58 AM
> >
> > @@ -82,6 +92,9 @@ static void __iommu_free_desc(struct ioptdesc *iopt)
> > struct folio *folio = ioptdesc_folio(iopt);
> > const unsigned long pgcnt = 1UL << folio_order(folio);
> >
> > + if (!IS_ENABLED(CONFIG_X86))
> > + WARN_ON_ONCE(iopt->incoherent);
> > +
>
> a comment is welcomed here.
How about this instead:
- if (!IS_ENABLED(CONFIG_X86))
+ if (IOMMU_PAGES_USE_DMA_API)
WARN_ON_ONCE(iopt->incoherent);
And all the other CONFIG_X86 removed
> > +/**
> > + * iommu_pages_start_incoherent - Setup the page for cache incoherent
> > operation
> > + * @virt: The page to setup
> > + * @dma_dev: The iommu device
> > + *
> > + * For incoherent memory we use the DMA API to manage the cache
> > flushing. This
> > + * is a lot of complexity compared to just calling
> > arch_sync_dma_for_device(),
> > + * but it is what the existing ARM iommu drivers have been doing. This
> > keeps
> > + * track of the dma map inside the ioptdesc so that error paths are simple
> > for
> > + * the caller.
> > + */
>
> also talk about the x86 specific case.
/**
* iommu_pages_start_incoherent - Setup the page for cache incoherent operation
* @virt: The page to setup
* @dma_dev: The iommu device
*
* For incoherent memory this will use the DMA API to manage the cache flushing
* on some arches. This is a lot of complexity compared to just calling
* arch_sync_dma_for_device(), but it is what the existing ARM iommu drivers
* have been doing. The DMA API requires keeping track of the DMA map and
* freeing it when required. This keeps track of the dma map inside the ioptdesc
* so that error paths are simple for the caller.
*/
> > +int iommu_pages_start_incoherent_list(struct iommu_pages_list *list,
> > + struct device *dma_dev)
> > +{
> > + struct ioptdesc *cur;
> > + int ret;
> > +
> > + list_for_each_entry(cur, &list->pages, iopt_freelist_elm) {
> > + if (cur->incoherent)
> > + continue;
>
> Is it a valid case to have the caller pass in a page which is already
> made incoherent?
I think no, I made it into a warn_on and will find out :)
> If yes the current definition of start/stop is not strictly no par, as
> there is no record whether item->incoherent is set in this start
> call or left over from previous call in a failure path. Then the caller
> just passes in the same list to stop to cleanup which reverts all
> items with incoherent in the list i.e. more that what a failed start
> may change.
But this would still be desired because the point of stop is
basically to prepare to free the list. It is structured like this
because we have to pass in the struct device * to call the DMA API..
Thanks,
Jason
next prev parent reply other threads:[~2025-08-22 21:13 UTC|newest]
Thread overview: 35+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-07-16 19:57 [PATCH 0/9] Convert Intel VT-D to use the generic iommu page table Jason Gunthorpe
2025-07-16 19:57 ` [PATCH 1/9] iommu/pages: Add support for a incoherent IOMMU page walker Jason Gunthorpe
2025-07-21 8:41 ` Baolu Lu
2025-07-29 22:32 ` Jason Gunthorpe
2025-07-30 1:49 ` Baolu Lu
2025-08-11 21:21 ` Jason Gunthorpe
2025-08-15 11:28 ` Tian, Kevin
2025-08-22 21:13 ` Jason Gunthorpe [this message]
2025-07-16 19:57 ` [PATCH 2/9] iommupt: Add basic support for SW bits in the page table Jason Gunthorpe
2025-08-15 11:29 ` Tian, Kevin
2025-08-18 23:35 ` Jason Gunthorpe
2025-07-16 19:57 ` [PATCH 3/9] iommupt: Use the incoherent start/stop functions for PT_FEAT_DMA_INCOHERENT Jason Gunthorpe
2025-08-15 11:35 ` Tian, Kevin
2025-08-22 20:45 ` Jason Gunthorpe
2025-07-16 19:57 ` [PATCH 4/9] iommupt: Flush the CPU cache after any writes to the page table Jason Gunthorpe
2025-07-16 19:57 ` [PATCH 5/9] iommupt: Add the Intel VT-D second stage page table format Jason Gunthorpe
2025-07-22 3:11 ` Baolu Lu
2025-07-29 23:05 ` Jason Gunthorpe
2025-07-30 2:00 ` Baolu Lu
2025-08-22 9:14 ` Tian, Kevin
2025-08-22 14:53 ` Jason Gunthorpe
2025-07-16 19:57 ` [PATCH 6/9] iommupt/x86: Set the dirty bit only for writable PTEs Jason Gunthorpe
2025-07-21 10:02 ` Baolu Lu
2025-07-16 19:57 ` [PATCH 7/9] iommupt/x86: Support SW bits and permit PT_FEAT_DMA_INCOHERENT Jason Gunthorpe
2025-07-22 5:17 ` Baolu Lu
2025-07-29 23:13 ` Jason Gunthorpe
2025-07-30 2:35 ` Baolu Lu
2025-08-22 9:17 ` Tian, Kevin
2025-08-22 14:55 ` Jason Gunthorpe
2025-07-16 19:57 ` [PATCH 8/9] iommu/vt-d: Use the generic iommu page table Jason Gunthorpe
2025-07-22 6:44 ` Baolu Lu
2025-07-29 23:39 ` Jason Gunthorpe
2025-08-22 9:35 ` Tian, Kevin
2025-08-22 20:43 ` Jason Gunthorpe
2025-07-16 19:57 ` [PATCH 9/9] iommupt: Add a kunit test for the SW bits Jason Gunthorpe
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