From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 363EB268C40; Tue, 26 Aug 2025 13:10:25 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1756213825; cv=none; b=rHYAnhhLniWwJpoQBB29Xm+QvjX21ERXIr7ioV7a4Dpy5JLJSQwiKAJedods3cl0fNE41/Zg77rzUSeNgwT4IagRRanfZY8qvMHY1AgVMgLC+5oZKdXKfDqix47Mb26ZHX+3eIC+5/wDEd71w1fdxoSpVXv+exBHkYam4uxDw4o= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1756213825; c=relaxed/simple; bh=cPXC9+gnmsTZZl0b/NgH+oqgXtrzkaVvrhyjEAL1KlY=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=t+TCcD3+IDMJg5IGTDxXCRpuYpL9GCa3Thvmlb6mL3CUvm2RQ5rXWlv3UVQ03cwe3bUusQHn8h6LpAtJ9cgT2L0Q8TjveIbboYVlz9APlG3u71rS/u8wtdTQQ2ZfIaqjfmdYbfs0IwJKW31Z+WJz82E87dj+bS2IZUlp2eVJIns= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=linuxfoundation.org header.i=@linuxfoundation.org header.b=wBpGutk0; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=linuxfoundation.org header.i=@linuxfoundation.org header.b="wBpGutk0" Received: by smtp.kernel.org (Postfix) with ESMTPSA id B596BC4CEF1; Tue, 26 Aug 2025 13:10:24 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=linuxfoundation.org; s=korg; t=1756213825; bh=cPXC9+gnmsTZZl0b/NgH+oqgXtrzkaVvrhyjEAL1KlY=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=wBpGutk0Gh/GM6WQPj2oGBe54udZxM37kP8I8WnMfMPQY0w3vREB/YUVVneDkmsws RVHwJ42NxblQBCso8cgG1DGXuL6uU95Z8/dXD/UIxOv8uBnN+VaYQTmNVN96iWAGYA WUOoqao9+gxQdGjqMiI8x5CrTzvx6qNQ2lzWQbtM= From: Greg Kroah-Hartman To: stable@vger.kernel.org Cc: Greg Kroah-Hartman , patches@lists.linux.dev, Geraldo Nascimento , Manivannan Sadhasivam , Bjorn Helgaas , Robin Murphy , Sasha Levin Subject: [PATCH 6.6 494/587] PCI: rockchip: Set Target Link Speed to 5.0 GT/s before retraining Date: Tue, 26 Aug 2025 13:10:43 +0200 Message-ID: <20250826111005.546560656@linuxfoundation.org> X-Mailer: git-send-email 2.50.1 In-Reply-To: <20250826110952.942403671@linuxfoundation.org> References: <20250826110952.942403671@linuxfoundation.org> User-Agent: quilt/0.68 X-stable: review X-Patchwork-Hint: ignore Precedence: bulk X-Mailing-List: patches@lists.linux.dev List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit 6.6-stable review patch. If anyone has any objections, please let me know. ------------------ From: Geraldo Nascimento [ Upstream commit 114b06ee108cabc82b995fbac6672230a9776936 ] Rockchip controllers can support up to 5.0 GT/s link speed. But the driver doesn't set the Target Link Speed currently. This may cause failure in retraining the link to 5.0 GT/s if supported by the endpoint. So set the Target Link Speed to 5.0 GT/s in the Link Control and Status Register 2. Fixes: e77f847df54c ("PCI: rockchip: Add Rockchip PCIe controller support") Signed-off-by: Geraldo Nascimento [mani: fixed whitespace warning, commit message rewording, added fixes tag] Signed-off-by: Manivannan Sadhasivam Signed-off-by: Bjorn Helgaas Tested-by: Robin Murphy Cc: stable@vger.kernel.org Link: https://patch.msgid.link/0afa6bc47b7f50e2e81b0b47d51c66feb0fb565f.1751322015.git.geraldogabriel@gmail.com Signed-off-by: Sasha Levin Signed-off-by: Greg Kroah-Hartman --- drivers/pci/controller/pcie-rockchip-host.c | 4 ++++ 1 file changed, 4 insertions(+) --- a/drivers/pci/controller/pcie-rockchip-host.c +++ b/drivers/pci/controller/pcie-rockchip-host.c @@ -339,6 +339,10 @@ static int rockchip_pcie_host_init_port( * Enable retrain for gen2. This should be configured only after * gen1 finished. */ + status = rockchip_pcie_read(rockchip, PCIE_RC_CONFIG_CR + PCI_EXP_LNKCTL2); + status &= ~PCI_EXP_LNKCTL2_TLS; + status |= PCI_EXP_LNKCTL2_TLS_5_0GT; + rockchip_pcie_write(rockchip, status, PCIE_RC_CONFIG_CR + PCI_EXP_LNKCTL2); status = rockchip_pcie_read(rockchip, PCIE_RC_CONFIG_CR + PCI_EXP_LNKCTL); status |= PCI_EXP_LNKCTL_RL; rockchip_pcie_write(rockchip, status, PCIE_RC_CONFIG_CR + PCI_EXP_LNKCTL);