From: hans.zhang@cixtech.com
To: bhelgaas@google.com, lpieralisi@kernel.org, kw@linux.com,
mani@kernel.org, robh@kernel.org, kwilczynski@kernel.org,
krzk+dt@kernel.org, conor+dt@kernel.org
Cc: mpillai@cadence.com, fugang.duan@cixtech.com,
guoyin.chen@cixtech.com, peter.chen@cixtech.com,
cix-kernel-upstream@cixtech.com, linux-pci@vger.kernel.org,
devicetree@vger.kernel.org, linux-kernel@vger.kernel.org,
Hans Zhang <hans.zhang@cixtech.com>
Subject: [PATCH v9 08/14] PCI: cadence: Update PCIe platform to use register offsets passed
Date: Mon, 1 Sep 2025 17:20:46 +0800 [thread overview]
Message-ID: <20250901092052.4051018-9-hans.zhang@cixtech.com> (raw)
In-Reply-To: <20250901092052.4051018-1-hans.zhang@cixtech.com>
From: Manikandan K Pillai <mpillai@cadence.com>
Update the PCIe Cadence platform to use register offsets that
are passed during probe of the platform.
Signed-off-by: Manikandan K Pillai <mpillai@cadence.com>
Co-developed-by: Hans Zhang <hans.zhang@cixtech.com>
Signed-off-by: Hans Zhang <hans.zhang@cixtech.com>
---
drivers/pci/controller/cadence/pcie-cadence-plat.c | 11 +++++++++++
1 file changed, 11 insertions(+)
diff --git a/drivers/pci/controller/cadence/pcie-cadence-plat.c b/drivers/pci/controller/cadence/pcie-cadence-plat.c
index b067a3296dd3..927ab5b8477c 100644
--- a/drivers/pci/controller/cadence/pcie-cadence-plat.c
+++ b/drivers/pci/controller/cadence/pcie-cadence-plat.c
@@ -31,6 +31,7 @@ static u64 cdns_plat_cpu_addr_fixup(struct cdns_pcie *pcie, u64 cpu_addr)
static const struct cdns_pcie_ops cdns_plat_ops = {
.cpu_addr_fixup = cdns_plat_cpu_addr_fixup,
+ .link_up = cdns_pcie_linkup,
};
static int cdns_plat_pcie_probe(struct platform_device *pdev)
@@ -68,6 +69,11 @@ static int cdns_plat_pcie_probe(struct platform_device *pdev)
rc = pci_host_bridge_priv(bridge);
rc->pcie.dev = dev;
rc->pcie.ops = &cdns_plat_ops;
+ rc->pcie.is_rc = data->is_rc;
+
+ /* Store the register bank offsets pointer */
+ rc->pcie.cdns_pcie_reg_offsets = data;
+
cdns_plat_pcie->pcie = &rc->pcie;
ret = cdns_pcie_init_phy(dev, cdns_plat_pcie->pcie);
@@ -95,6 +101,11 @@ static int cdns_plat_pcie_probe(struct platform_device *pdev)
ep->pcie.dev = dev;
ep->pcie.ops = &cdns_plat_ops;
+ ep->pcie.is_rc = data->is_rc;
+
+ /* Store the register bank offset pointer */
+ ep->pcie.cdns_pcie_reg_offsets = data;
+
cdns_plat_pcie->pcie = &ep->pcie;
ret = cdns_pcie_init_phy(dev, cdns_plat_pcie->pcie);
--
2.49.0
next prev parent reply other threads:[~2025-09-01 9:21 UTC|newest]
Thread overview: 27+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-09-01 9:20 [PATCH v9 00/14] Enhance the PCIe controller driver for next generation controllers hans.zhang
2025-09-01 9:20 ` [PATCH v9 01/14] PCI: cadence: Add module support for platform controller driver hans.zhang
2025-09-01 9:20 ` [PATCH v9 02/14] PCI: cadence: Split PCIe controller header file hans.zhang
2025-09-01 9:20 ` [PATCH v9 03/14] PCI: cadence: Add register definitions for High Perf Architecture (HPA) hans.zhang
2025-09-08 10:22 ` Manivannan Sadhasivam
2025-09-08 11:02 ` Manikandan Karunakaran Pillai
2025-09-15 3:43 ` Manikandan Karunakaran Pillai
2025-09-15 5:32 ` Manivannan Sadhasivam
2025-09-01 9:20 ` [PATCH v9 04/14] PCI: cadence: Add helper functions for supporting " hans.zhang
2025-09-08 10:23 ` Manivannan Sadhasivam
2025-09-08 11:03 ` Manikandan Karunakaran Pillai
2025-09-01 9:20 ` [PATCH v9 05/14] PCI: cadence: Move PCIe EP common functions to a separate file hans.zhang
2025-09-08 10:24 ` Manivannan Sadhasivam
2025-09-01 9:20 ` [PATCH v9 06/14] PCI: cadence: Move PCIe RP " hans.zhang
2025-09-01 9:20 ` [PATCH v9 07/14] PCI: cadence: Add support for High Perf Architecture (HPA) controller hans.zhang
2025-09-08 11:28 ` Manivannan Sadhasivam
2025-09-08 16:41 ` Hans Zhang
2025-09-15 5:49 ` Manivannan Sadhasivam
2025-09-01 9:20 ` hans.zhang [this message]
2025-09-01 9:20 ` [PATCH v9 09/14] dt-bindings: PCI: Add CIX Sky1 PCIe Root Complex bindings hans.zhang
2025-09-01 9:20 ` [PATCH v9 10/14] PCI: Add Cix Technology Vendor and Device ID hans.zhang
2025-09-01 9:20 ` [PATCH v9 11/14] PCI: sky1: Add PCIe host support for CIX Sky1 hans.zhang
2025-09-01 9:20 ` [PATCH v9 12/14] MAINTAINERS: add entry for CIX Sky1 PCIe driver hans.zhang
2025-09-01 9:20 ` [PATCH v9 13/14] arm64: dts: cix: Add PCIe Root Complex on sky1 hans.zhang
2025-09-01 9:20 ` [PATCH v9 14/14] arm64: dts: cix: Enable PCIe on the Orion O6 board hans.zhang
2025-10-19 5:50 ` [PATCH v9 00/14] Enhance the PCIe controller driver for next generation controllers Manivannan Sadhasivam
2025-10-19 6:29 ` Manikandan Karunakaran Pillai
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=20250901092052.4051018-9-hans.zhang@cixtech.com \
--to=hans.zhang@cixtech.com \
--cc=bhelgaas@google.com \
--cc=cix-kernel-upstream@cixtech.com \
--cc=conor+dt@kernel.org \
--cc=devicetree@vger.kernel.org \
--cc=fugang.duan@cixtech.com \
--cc=guoyin.chen@cixtech.com \
--cc=krzk+dt@kernel.org \
--cc=kw@linux.com \
--cc=kwilczynski@kernel.org \
--cc=linux-kernel@vger.kernel.org \
--cc=linux-pci@vger.kernel.org \
--cc=lpieralisi@kernel.org \
--cc=mani@kernel.org \
--cc=mpillai@cadence.com \
--cc=peter.chen@cixtech.com \
--cc=robh@kernel.org \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is an external index of several public inboxes,
see mirroring instructions on how to clone and mirror
all data and code used by this external index.