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Tsirkin" , "Marcel Apfelbaum" , , , , Wilfred Mallawa Subject: Re: [PATCH v4 3/5] hw/nvme: add NVMe Admin Security SPDM support Message-ID: <20250904112205.00007e47@huawei.com> In-Reply-To: <20250904031058.367667-5-wilfred.opensource@gmail.com> References: <20250904031058.367667-2-wilfred.opensource@gmail.com> <20250904031058.367667-5-wilfred.opensource@gmail.com> X-Mailer: Claws Mail 4.3.0 (GTK 3.24.42; x86_64-w64-mingw32) MIME-Version: 1.0 Content-Type: text/plain; charset="US-ASCII" Content-Transfer-Encoding: 7bit X-Originating-IP: [10.203.177.15] X-ClientProxiedBy: lhrpeml100012.china.huawei.com (7.191.174.184) To frapeml500008.china.huawei.com (7.182.85.71) X-Host-Lookup-Failed: Reverse DNS lookup failed for 185.176.79.56 (deferred) Received-SPF: pass client-ip=185.176.79.56; envelope-from=jonathan.cameron@huawei.com; helo=frasgout.his.huawei.com X-Spam_score_int: -33 X-Spam_score: -3.4 X-Spam_bar: --- X-Spam_report: (-3.4 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_DNSWL_MED=-2.3, RCVD_IN_MSPIKE_H4=0.001, RCVD_IN_MSPIKE_WL=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001, RDNS_NONE=0.793, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Reply-to: Jonathan Cameron From: Jonathan Cameron via Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org On Thu, 4 Sep 2025 13:10:57 +1000 Wilfred Mallawa wrote: > From: Wilfred Mallawa > > Adds the NVMe Admin Security Send/Receive command support with support > for DMTFs SPDM. The transport binding for SPDM is defined in the > DMTF DSP0286. > > Signed-off-by: Wilfred Mallawa Hi Wilfred, I haven't even opened the nvme spec on basis others are covering that part well. So this is just a review based on the code in this patch so mostly style stuff. Jonathan > --- > hw/nvme/ctrl.c | 213 ++++++++++++++++++++++++++++++++++++++++++- > hw/nvme/nvme.h | 5 + > include/block/nvme.h | 15 +++ > 3 files changed, 232 insertions(+), 1 deletion(-) > > diff --git a/hw/nvme/ctrl.c b/hw/nvme/ctrl.c > index f5ee6bf260..df72599bcc 100644 > --- a/hw/nvme/ctrl.c > +++ b/hw/nvme/ctrl.c > @@ -282,6 +282,8 @@ static const uint32_t nvme_cse_acs_default[256] = { > [NVME_ADM_CMD_FORMAT_NVM] = NVME_CMD_EFF_CSUPP | NVME_CMD_EFF_LBCC, > [NVME_ADM_CMD_DIRECTIVE_RECV] = NVME_CMD_EFF_CSUPP, > [NVME_ADM_CMD_DIRECTIVE_SEND] = NVME_CMD_EFF_CSUPP, > + [NVME_ADM_CMD_SECURITY_SEND] = NVME_CMD_EFF_CSUPP, > + [NVME_ADM_CMD_SECURITY_RECV] = NVME_CMD_EFF_CSUPP, Maybe it's an email thing but that alignment of = looks off by one space. > }; > > static const uint32_t nvme_cse_iocs_nvm_default[256] = { > @@ -7282,6 +7284,210 @@ static uint16_t nvme_dbbuf_config(NvmeCtrl *n, const NvmeRequest *req) > return NVME_SUCCESS; > } > > +static uint16_t nvme_sec_prot_spdm_send(NvmeCtrl *n, NvmeRequest *req) > +{ > + StorageSpdmTransportHeader hdr = {0}; > + g_autofree uint8_t *sec_buf = NULL; > + uint32_t transfer_len = le32_to_cpu(req->cmd.cdw11); > + uint32_t transport_transfer_len = transfer_len; > + uint32_t dw10 = le32_to_cpu(req->cmd.cdw10); > + uint32_t recvd; > + uint16_t nvme_cmd_status, ret; > + uint8_t secp = extract32(dw10, 24, 8); > + uint8_t spsp1 = extract32(dw10, 16, 8); > + uint8_t spsp0 = extract32(dw10, 8, 8); See below. 16 bit field seems more logical to me. > + bool spdm_res; > + > + if (transport_transfer_len > UINT32_MAX - sizeof(hdr)) { > + return NVME_INVALID_FIELD | NVME_DNR; > + } > + > + transport_transfer_len += sizeof(hdr); > + if (transport_transfer_len > SPDM_SOCKET_MAX_MESSAGE_BUFFER_SIZE) { > + return NVME_INVALID_FIELD | NVME_DNR; > + } > + > + ret = nvme_check_mdts(n, transport_transfer_len); > + if (ret != NVME_SUCCESS) { > + return ret; > + } > + > + /* Generate the NVMe transport header */ > + hdr.security_protocol = secp; > + hdr.security_protocol_specific = cpu_to_le16((spsp1 << 8) | spsp0); > + hdr.length = cpu_to_le32(transfer_len); > + > + sec_buf = g_try_malloc0(transport_transfer_len); > + if (!sec_buf) { > + return NVME_INTERNAL_DEV_ERROR; > + } > + > + /* Attach the transport header */ > + memcpy(sec_buf, &hdr, sizeof(hdr)); > + ret = nvme_h2c(n, sec_buf + sizeof(hdr), transfer_len, req); > + if (ret) { > + return ret; > + } > + > + spdm_res = spdm_socket_send(n->spdm_socket, SPDM_SOCKET_STORAGE_CMD_IF_SEND, > + SPDM_SOCKET_TRANSPORT_TYPE_NVME, sec_buf, > + transport_transfer_len); > + if (!spdm_res) { > + return NVME_DATA_TRAS_ERROR | NVME_DNR; > + } > + > + /* The responder shall ack with message status */ > + recvd = spdm_socket_receive(n->spdm_socket, SPDM_SOCKET_TRANSPORT_TYPE_NVME, > + (uint8_t *)&nvme_cmd_status, As in earlier patch, spdm_socket_receive() seems to take a void * so no cast should be needed and definitely not to a uint8_t *! > + SPDM_SOCKET_MAX_MSG_STATUS_LEN); > + > + nvme_cmd_status = be16_to_cpu(nvme_cmd_status); > + > + if (recvd < SPDM_SOCKET_MAX_MSG_STATUS_LEN) { > + return NVME_DATA_TRAS_ERROR | NVME_DNR; > + } > + > + return nvme_cmd_status; > +} > + > +/* From host to controller */ > +static uint16_t nvme_security_send(NvmeCtrl *n, NvmeRequest *req) > +{ > + uint32_t dw10 = le32_to_cpu(req->cmd.cdw10); > + uint8_t secp = (dw10 >> 24) & 0xff; Used extract32() below. Why not for this one? > + > + switch (secp) { > + case NVME_SEC_PROT_DMTF_SPDM: > + if (n->spdm_socket <= 0) { > + return NVME_INVALID_FIELD | NVME_DNR; > + } > + return nvme_sec_prot_spdm_send(n, req); > + default: > + /* Unsupported Security Protocol Type */ > + return NVME_INVALID_FIELD | NVME_DNR; > + } > + > + return NVME_INVALID_FIELD | NVME_DNR; > +} > + > +static uint16_t nvme_sec_prot_spdm_receive(NvmeCtrl *n, NvmeRequest *req) > +{ > + StorageSpdmTransportHeader hdr; > + g_autofree uint8_t *rsp_spdm_buf = NULL; > + uint32_t dw10 = le32_to_cpu(req->cmd.cdw10); > + uint32_t alloc_len = le32_to_cpu(req->cmd.cdw11); > + uint32_t recvd, spdm_res; > + uint16_t nvme_cmd_status, ret; > + uint8_t secp = extract32(dw10, 24, 8); > + uint8_t spsp1 = extract32(dw10, 16, 8); > + uint8_t spsp0 = extract32(dw10, 8, 8); This is a little odd. You break out two 8 bit fields here just to combine them again below. Why not a 16bit field? If its about spec alignment maybe call that field spsp0_1 > + > + if (!alloc_len) { > + return NVME_INVALID_FIELD | NVME_DNR; > + } > + > + /* Generate the NVMe transport header */ > + hdr = (StorageSpdmTransportHeader) { > + .security_protocol = secp, > + .security_protocol_specific = cpu_to_le16((spsp1 << 8) | spsp0), > + .length = cpu_to_le32(alloc_len), > + }; > + > + /* Forward if_recv to the SPDM Server with SPSP0 */ > + spdm_res = spdm_socket_send(n->spdm_socket, SPDM_SOCKET_STORAGE_CMD_IF_RECV, > + SPDM_SOCKET_TRANSPORT_TYPE_NVME, > + (uint8_t *)&hdr, sizeof(hdr)); As above. > + if (!spdm_res) { > + return NVME_DATA_TRAS_ERROR | NVME_DNR; > + } > + > + /* The responder shall ack with message status */ > + recvd = spdm_socket_receive(n->spdm_socket, SPDM_SOCKET_TRANSPORT_TYPE_NVME, > + (uint8_t *)&nvme_cmd_status, As above - seems to be a spurious cast. > + SPDM_SOCKET_MAX_MSG_STATUS_LEN);