From: dmukhin@xen.org
To: xen-devel@lists.xenproject.org
Cc: andrew.cooper3@citrix.com, anthony.perard@vates.tech,
jbeulich@suse.com, julien@xen.org, michal.orzel@amd.com,
roger.pau@citrix.com, sstabellini@kernel.org, dmukhin@ford.com
Subject: [PATCH v7 09/16] emul/ns16x50: implement RBR register
Date: Mon, 8 Sep 2025 14:11:42 -0700 [thread overview]
Message-ID: <20250908211149.279143-10-dmukhin@ford.com> (raw)
In-Reply-To: <20250908211149.279143-1-dmukhin@ford.com>
From: Denis Mukhin <dmukhin@ford.com>
Add RBR register emulation to the I/O port handlder.
Add RX FIFO management code since RBR depends on RX FIFO.
RX FIFO is not emulated as per UART specs for simplicity (not need to emulate
baud rate). Emulator does not emulate NS8250 (no FIFO), NS16550a (16 bytes) or
NS16750 (64 bytes).
RX FIFO is emulated by means of using xencons_interface which conveniently
provides primitives for buffer management and later can be used for
inter-domain communication similarly to vpl011.
Account for DLL == 0: in this case, disable receiver.
Add UART_LSR_DR handling since it depends on RBR register access.
Finally, implement put_rx() vUART hook for placing a character into the
emulated RX FIFO from console driver. That implements physical console
forwarding to the guest OS over emulated NS16550.
Signed-off-by: Denis Mukhin <dmukhin@ford.com>
---
Changes since v6:
- added DLL == 0 case handling as per Mykola's suggestion
---
xen/common/emul/vuart/ns16x50.c | 134 +++++++++++++++++++++++++++++++-
1 file changed, 132 insertions(+), 2 deletions(-)
diff --git a/xen/common/emul/vuart/ns16x50.c b/xen/common/emul/vuart/ns16x50.c
index fdc20124d4c9..250411e0a7d8 100644
--- a/xen/common/emul/vuart/ns16x50.c
+++ b/xen/common/emul/vuart/ns16x50.c
@@ -9,6 +9,8 @@
* https://www.ti.com/lit/ds/symlink/tl16c550c.pdf
* - UART w/ 64 byte FIFO:
* https://www.ti.com/lit/ds/symlink/tl16c750.pdf
+ * - DesignWare DW_apb_uart Databook, v4.02a:
+ * https://iccircle.com/static/upload/img20240313113905.pdf
*
* Limitations:
* - Only x86;
@@ -85,6 +87,74 @@ struct vuart_ns16x50 {
struct xencons_interface cons; /* Emulated RX/TX FIFOs */
};
+static bool ns16x50_fifo_rx_empty(const struct vuart_ns16x50 *vdev)
+{
+ const struct xencons_interface *cons = &vdev->cons;
+
+ return cons->in_prod == cons->in_cons;
+}
+
+static bool ns16x50_fifo_rx_full(const struct vuart_ns16x50 *vdev)
+{
+ const struct xencons_interface *cons = &vdev->cons;
+
+ return cons->in_prod - cons->in_cons == ARRAY_SIZE(cons->in);
+}
+
+static void ns16x50_fifo_rx_reset(struct vuart_ns16x50 *vdev)
+{
+ struct xencons_interface *cons = &vdev->cons;
+
+ cons->in_cons = cons->in_prod;
+}
+
+/*
+ * Transfer character from RX FIFO and return the RX FIFO status after the
+ * transfer.
+ */
+static int ns16x50_fifo_rx_getchar(struct vuart_ns16x50 *vdev, uint8_t *ptr)
+{
+ struct xencons_interface *cons = &vdev->cons;
+
+ if ( ns16x50_fifo_rx_empty(vdev) )
+ return -ENODATA;
+
+ *ptr = cons->in[MASK_XENCONS_IDX(cons->in_cons, cons->in)];
+ cons->in_cons++;
+
+ return ns16x50_fifo_rx_empty(vdev) ? -ENODATA : 0;
+}
+
+static int ns16x50_fifo_rx_putchar(struct vuart_ns16x50 *vdev, char c)
+{
+ struct xencons_interface *cons = &vdev->cons;
+ int rc;
+
+ /*
+ * FIFO-less 8250/16450 UARTs: newly arrived word overwrites the contents
+ * of the THR.
+ */
+ if ( ns16x50_fifo_rx_full(vdev) )
+ {
+ ns16x50_debug(vdev, "RX FIFO full; resetting\n");
+ ns16x50_fifo_rx_reset(vdev);
+ rc = -ENOSPC;
+ }
+ else
+ rc = 0;
+
+ cons->in[MASK_XENCONS_IDX(cons->in_prod, cons->in)] = c;
+ cons->in_prod++;
+
+ return rc;
+}
+
+static bool ns16x50_is_running(const struct vuart_ns16x50 *vdev)
+{
+ /* DLL set to 0 disables serial communication. */
+ return vdev->regs[NS16X50_REGS_NUM + UART_DLL];
+}
+
static uint8_t ns16x50_dlab_get(const struct vuart_ns16x50 *vdev)
{
return vdev->regs[UART_LCR] & UART_LCR_DLAB ? 1 : 0;
@@ -97,7 +167,7 @@ static bool cf_check ns16x50_iir_check_lsi(const struct vuart_ns16x50 *vdev)
static bool cf_check ns16x50_iir_check_rda(const struct vuart_ns16x50 *vdev)
{
- return false;
+ return !ns16x50_fifo_rx_empty(vdev);
}
static bool cf_check ns16x50_iir_check_thr(const struct vuart_ns16x50 *vdev)
@@ -362,6 +432,20 @@ static int ns16x50_io_read8(
{
switch ( reg )
{
+ case UART_RBR:
+ if ( !ns16x50_is_running(vdev) )
+ break;
+
+ /* NB: do not forget to clear overrun condition */
+ regs[UART_LSR] &= ~UART_LSR_OE;
+
+ if ( ns16x50_fifo_rx_getchar(vdev, &val) )
+ regs[UART_LSR] &= ~UART_LSR_DR;
+ else
+ regs[UART_LSR] |= UART_LSR_DR;
+
+ break;
+
case UART_IER:
val = regs[UART_IER];
break;
@@ -611,13 +695,59 @@ static void cf_check ns16x50_free(void *arg)
xvfree(arg);
}
+static int cf_check ns16x50_put_rx(void *arg, char ch)
+{
+ struct vuart_ns16x50 *vdev = arg;
+ uint8_t *regs;
+ uint8_t dlab;
+ int rc = -EBUSY;
+
+ spin_lock(&vdev->lock);
+
+ dlab = ns16x50_dlab_get(vdev);
+ regs = vdev->regs;
+
+ if ( !ns16x50_is_running(vdev) )
+ ns16x50_debug(vdev, "THR/RBR access disabled: DLL == 0\n");
+ else if ( dlab )
+ ns16x50_debug(vdev, "THR/RBR access disabled: DLAB=1\n");
+ else if ( regs[UART_MCR] & UART_MCR_LOOP )
+ ns16x50_debug(vdev, "THR/RBR access disabled: loopback mode\n");
+ else
+ {
+ const struct domain *d = vdev->owner;
+
+ /*
+ * Echo the user input on Xen console iff Xen console input is owned
+ * by ns16x50 domain.
+ * NB: use 'console_timestamps=none' to disable Xen timestamps.
+ */
+ if ( is_console_printable(ch) )
+ guest_printk(d, "%c", ch);
+
+ if ( ns16x50_fifo_rx_putchar(vdev, ch) )
+ regs[UART_LSR] |= UART_LSR_OE;
+
+ regs[UART_LSR] |= UART_LSR_DR;
+
+ /* TODO: check FCR when to fire an interrupt */
+ ns16x50_irq_check(vdev);
+
+ rc = 0;
+ }
+
+ spin_unlock(&vdev->lock);
+
+ return rc;
+}
+
#define ns16x50_emulator \
{ \
.compatible = "ns16550", \
.alloc = ns16x50_alloc, \
.free = ns16x50_free, \
.dump_state = NULL, \
- .put_rx = NULL, \
+ .put_rx = ns16x50_put_rx, \
}
VUART_REGISTER(ns16x50, ns16x50_emulator);
--
2.51.0
next prev parent reply other threads:[~2025-09-08 21:12 UTC|newest]
Thread overview: 46+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-09-08 21:11 [PATCH v7 00/16] x86: introduce NS16550-compatible UART emulator dmukhin
2025-09-08 21:11 ` [PATCH v7 01/16] emul/vuart: introduce framework for UART emulators dmukhin
2025-09-10 7:57 ` Mykola Kvach
2025-09-13 18:09 ` dmukhin
2025-09-08 21:11 ` [PATCH v7 02/16] xen/8250-uart: update definitions dmukhin
2025-09-09 10:05 ` Jan Beulich
2025-09-09 19:42 ` dmukhin
2025-09-10 8:39 ` Mykola Kvach
2025-09-13 17:50 ` dmukhin
2025-09-08 21:11 ` [PATCH v7 03/16] emul/ns16x50: implement emulator stub dmukhin
2025-09-10 10:05 ` Mykola Kvach
2025-09-13 17:29 ` dmukhin
2025-11-14 5:19 ` dmukhin
2025-09-15 10:16 ` Mykola Kvach
2025-11-14 5:28 ` dmukhin
2025-09-08 21:11 ` [PATCH v7 04/16] emul/ns16x50: implement DLL/DLM registers dmukhin
2025-09-10 10:16 ` Mykola Kvach
2025-09-08 21:11 ` [PATCH v7 05/16] emul/ns16x50: implement SCR register dmukhin
2025-09-12 7:23 ` Mykola Kvach
2025-09-08 21:11 ` [PATCH v7 06/16] emul/ns16x50: implement IER/IIR registers dmukhin
2025-09-15 6:00 ` Mykola Kvach
2025-09-08 21:11 ` [PATCH v7 07/16] emul/ns16x50: implement LCR/LSR registers dmukhin
2025-09-15 6:00 ` Mykola Kvach
2025-09-08 21:11 ` [PATCH v7 08/16] emul/ns16x50: implement MCR/MSR registers dmukhin
2025-09-15 6:00 ` Mykola Kvach
2025-09-15 14:49 ` Jan Beulich
2025-09-16 8:00 ` Mykola Kvach
2025-09-16 14:13 ` Jan Beulich
2025-09-08 21:11 ` dmukhin [this message]
2025-11-18 6:00 ` [PATCH v7 09/16] emul/ns16x50: implement RBR register Mykola Kvach
2025-09-08 21:11 ` [PATCH v7 10/16] emul/ns16x50: implement THR register dmukhin
2025-11-18 6:00 ` Mykola Kvach
2026-05-14 23:23 ` dmukhin
2025-09-08 21:11 ` [PATCH v7 11/16] emul/ns16x50: implement FCR register (write-only) dmukhin
2025-11-18 6:00 ` Mykola Kvach
2025-09-08 21:11 ` [PATCH v7 12/16] emul/ns16550: implement dump_state() hook dmukhin
2025-11-18 6:00 ` Mykola Kvach
2026-05-14 23:35 ` dmukhin
2025-09-08 21:11 ` [PATCH v7 13/16] emul/ns16x50: add Kconfig options dmukhin
2025-11-18 6:00 ` Mykola Kvach
2025-09-08 21:11 ` [PATCH v7 14/16] x86/domain: enable per-domain I/O port bitmaps dmukhin
2025-11-18 6:00 ` Mykola Kvach
2026-05-14 23:52 ` dmukhin
2025-09-08 21:11 ` [PATCH v7 15/16] xen/domain: allocate d->irq_caps before arch-specific initialization dmukhin
2025-11-18 6:00 ` Mykola Kvach
2025-09-08 21:11 ` [PATCH v7 16/16] emul/ns16x50: implement IRQ emulation via vIOAPIC dmukhin
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