From: Jonathan Cameron <jonathan.cameron@huawei.com>
To: Robert Richter <rrichter@amd.com>
Cc: Alison Schofield <alison.schofield@intel.com>,
Vishal Verma <vishal.l.verma@intel.com>,
Ira Weiny <ira.weiny@intel.com>,
Dan Williams <dan.j.williams@intel.com>,
Dave Jiang <dave.jiang@intel.com>,
"Davidlohr Bueso" <dave@stgolabs.net>,
<linux-cxl@vger.kernel.org>, <linux-kernel@vger.kernel.org>,
Gregory Price <gourry@gourry.net>,
"Fabio M. De Francesco" <fabio.m.de.francesco@linux.intel.com>,
Terry Bowman <terry.bowman@amd.com>,
Joshua Hahn <joshua.hahnjy@gmail.com>
Subject: Re: [PATCH v3 11/11] cxl: Enable AMD Zen5 address translation using ACPI PRMT
Date: Wed, 17 Sep 2025 14:50:58 +0100 [thread overview]
Message-ID: <20250917145058.00006183@huawei.com> (raw)
In-Reply-To: <aMqCy670eTu-ZYUO@rric.localdomain>
On Wed, 17 Sep 2025 11:43:39 +0200
Robert Richter <rrichter@amd.com> wrote:
> On 15.09.25 11:59:48, Jonathan Cameron wrote:
> > On Fri, 12 Sep 2025 16:45:13 +0200
> > Robert Richter <rrichter@amd.com> wrote:
> >
> > > Add AMD Zen5 support for address translation.
> > >
> > > Zen5 systems may be configured to use 'Normalized addresses'. Then,
> > > CXL endpoints use their own physical address space and are programmed
> > > passthrough (DPA == HPA), the number of interleaving ways for the
> > > endpoint is set to one. The Host Physical Addresses (HPAs) need to be
> > > translated from the endpoint to its CXL host bridge. The HPA of a CXL
> > > host bridge is equivalent to the System Physical Address (SPA).
> > >
> > > ACPI Platform Runtime Mechanism (PRM) is used to translate the CXL
> > > Device Physical Address (DPA) to its System Physical Address. This is
> > > documented in:
> > >
> > > AMD Family 1Ah Models 00h–0Fh and Models 10h–1Fh
> > > ACPI v6.5 Porting Guide, Publication # 58088
> > > https://www.amd.com/en/search/documentation/hub.html
> > >
> > > To implement AMD Zen5 address translation the following steps are
> > > needed:
> > >
> > > AMD Zen5 systems support the ACPI PRM CXL Address Translation firmware
> > > call (Address Translation - CXL DPA to System Physical Address, see
> > > ACPI v6.5 Porting Guide above) when address translation is enabled.
> > > The existence of the callback can be identified using a specific GUID
> > > as documented. The initialization code checks firmware and kernel
> > > support of ACPI PRM.
> > >
> > > Introduce a new file core/atl.c to handle ACPI PRM specific address
> > > translation code. Naming is loosely related to the kernel's AMD
> > > Address Translation Library (CONFIG_AMD_ATL) but implementation does
> > > not dependent on it, nor it is vendor specific. Use Kbuild and Kconfig
> > > options respectively to enable the code depending on architecture and
> > > platform options.
> > >
> > > Implement an ACPI PRM firmware call for CXL address translation in the
> > > new function cxl_prm_to_hpa(). This includes sanity checks. Enable the
> > > callback for applicable CXL host bridges using the new cxl_atl_init()
> > > function.
> > >
> > > Signed-off-by: Robert Richter <rrichter@amd.com>
> > A few minor additions inline.
> >
> > J
> > > ---
> > > drivers/cxl/Kconfig | 4 ++
> > > drivers/cxl/core/Makefile | 1 +
> > > drivers/cxl/core/atl.c | 138 ++++++++++++++++++++++++++++++++++++++
> > > drivers/cxl/core/core.h | 1 +
> > > drivers/cxl/core/port.c | 8 +++
> > > 5 files changed, 152 insertions(+)
> > > create mode 100644 drivers/cxl/core/atl.c
> > >
> > > diff --git a/drivers/cxl/Kconfig b/drivers/cxl/Kconfig
> > > index 48b7314afdb8..31f9c96ef908 100644
> > > --- a/drivers/cxl/Kconfig
> > > +++ b/drivers/cxl/Kconfig
> > > @@ -233,4 +233,8 @@ config CXL_MCE
> > > def_bool y
> > > depends on X86_MCE && MEMORY_FAILURE
> > >
> > > +config CXL_ATL
> > > + def_bool y
> >
> > Given no help we can't turn this off manually and it's down to
> > whether ACPI_PRMT is configured or not.
> >
> > To me this feels like something we should be able to control.
> > Not a huge amount of code, but none the less 'so far' it only
> > applies to particular AMD platforms yet ACPI_PRMT gets built
> > on ARM platforms and other stuff even on AMD (CONFIG_AMD_ATL_PRM)
>
> How about default y where possible but have a menu entry to disable
> address translation?
>
> config CXL_ATL
> bool "CXL Address Translation support"
> default y
> depends on ACPI_PRMT
>
> I don't want to make it specific to AMD.
Can we drop the default y?
That feels to me like a defconfig thing rather than a thing we should
apply generally.
Also remember to add some detailed help text given it's now visible in
menuconfig etc.
>
> >
> >
> >
> > > + depends on ACPI_PRMT
> > > +
> > > endif
> >
> > > +static void cxl_prm_init(struct cxl_port *port)
> > > +{
> > > + u64 spa;
> > > + struct prm_cxl_dpa_spa_data data = { .out = &spa, };
> > > + int rc;
> > > +
> > > + if (!check_prm_address_translation(port))
> > > + return;
> > > +
> > > + /* Check kernel (-EOPNOTSUPP) and firmware support (-ENODEV) */
> > > + rc = acpi_call_prm_handler(prm_cxl_dpa_spa_guid, &data);
> > > + if (rc == -EOPNOTSUPP || rc == -ENODEV)
> > > + return;
> >
> > So other error values are fine? IF they don't occur no need to be explicit
> > just check rc < 0 and return.
>
> This is just to check the existence of the PRM, but it will fail (if
> exists) here as parameters are a stub only. Both error codes are
> reserved for firmware or kernel support respectively. Else, it returns
> the PRM's error code, which is ignored here.
Why is the PRM error code not something we want to pay attention to?
Perhaps that's the comment that is missing. I guess because we will
see any consistent failure later?
>
> >
> > > +
> > > + port->to_hpa = cxl_prm_to_hpa;
> > > +
> > > + dev_dbg(port->host_bridge, "PRM address translation enabled for %s.\n",
> > > + dev_name(&port->dev));
> > > +}
> > > +
> > > +void cxl_atl_init(struct cxl_port *port)
> > > +{
> > > + cxl_prm_init(port);
> > Why not just rename cxl_prm_init() to cxl_atl_init() and get rid of this wrapper?
>
> cxl_prm_init() handles the PRM specifics, while cxl_atl_init() is used
> as an entry for the core module to enable address translation. I
> thought it would be misleading to name cxl_prm_init() different. The
> compiler result should be the same for both.
Ok. I'm not sure it's worth the separation but as you say it'll almost
certainly get flattened anyway!
Jonathan
>
> -Robert
>
> >
> > > +}
> >
> >
next prev parent reply other threads:[~2025-09-17 13:51 UTC|newest]
Thread overview: 62+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-09-12 14:45 [PATCH v3 00/11] cxl: ACPI PRM Address Translation Support and AMD Zen5 enablement Robert Richter
2025-09-12 14:45 ` [PATCH v3 01/11] cxl/region: Store root decoder in struct cxl_region Robert Richter
2025-09-12 15:52 ` Dave Jiang
2025-09-15 10:14 ` Jonathan Cameron
2025-09-17 19:56 ` Gregory Price
2025-09-23 21:40 ` Alison Schofield
2025-09-26 17:52 ` Robert Richter
2025-09-12 14:45 ` [PATCH v3 02/11] cxl/region: Store HPA range " Robert Richter
2025-09-12 17:17 ` Dave Jiang
2025-09-15 7:19 ` Robert Richter
2025-09-15 16:24 ` Dave Jiang
2025-09-15 10:23 ` Jonathan Cameron
2025-09-17 8:15 ` Robert Richter
2025-09-17 19:58 ` Gregory Price
2025-09-12 14:45 ` [PATCH v3 03/11] cxl/region: Rename misleading variable name @hpa to @range Robert Richter
2025-09-12 17:33 ` Dave Jiang
2025-09-15 7:27 ` Robert Richter
2025-09-15 10:25 ` Jonathan Cameron
2025-09-17 8:10 ` Robert Richter
2025-09-17 20:01 ` Gregory Price
2025-09-12 14:45 ` [PATCH v3 04/11] cxl/region: Add @range argument to function cxl_find_root_decoder() Robert Richter
2025-09-17 20:05 ` Gregory Price
2025-09-12 14:45 ` [PATCH v3 05/11] cxl/region: Add @range argument to function cxl_calc_interleave_pos() Robert Richter
2025-09-17 20:09 ` Gregory Price
2025-09-23 21:52 ` Alison Schofield
2025-09-26 18:22 ` Robert Richter
2025-09-12 14:45 ` [PATCH v3 06/11] cxl/region: Separate region parameter setup and region construction Robert Richter
2025-09-12 21:10 ` Dave Jiang
2025-09-15 7:31 ` Robert Richter
2025-09-15 16:26 ` Dave Jiang
2025-09-17 20:15 ` Gregory Price
2025-09-12 14:45 ` [PATCH v3 07/11] cxl: Introduce callback to translate a decoder's HPA to the next parent port Robert Richter
2025-09-12 21:21 ` Dave Jiang
2025-09-15 7:55 ` Robert Richter
2025-09-15 16:32 ` Dave Jiang
2025-09-15 20:22 ` Dave Jiang
2025-09-17 8:20 ` Robert Richter
2025-09-12 14:45 ` [PATCH v3 08/11] cxl/region: Implement endpoint decoder address translation Robert Richter
2025-09-15 10:46 ` Jonathan Cameron
2025-09-15 16:35 ` Dave Jiang
2025-09-17 9:04 ` Robert Richter
2025-09-17 20:51 ` Gregory Price
2025-09-17 20:57 ` Dave Jiang
2025-09-18 13:59 ` Gregory Price
2025-09-12 14:45 ` [PATCH v3 09/11] cxl/region: Lock decoders that need " Robert Richter
2025-09-17 20:52 ` Gregory Price
2025-09-12 14:45 ` [PATCH v3 10/11] cxl/acpi: Prepare use of EFI runtime services Robert Richter
2025-09-17 20:54 ` Gregory Price
2025-09-12 14:45 ` [PATCH v3 11/11] cxl: Enable AMD Zen5 address translation using ACPI PRMT Robert Richter
2025-09-12 23:46 ` Dave Jiang
2025-09-15 8:34 ` Robert Richter
2025-09-15 10:59 ` Jonathan Cameron
2025-09-17 9:43 ` Robert Richter
2025-09-17 13:50 ` Jonathan Cameron [this message]
2025-09-17 21:01 ` Dave Jiang
2025-09-24 17:09 ` Gregory Price
2025-09-26 16:59 ` Robert Richter
2025-09-27 1:44 ` Gregory Price
2025-09-29 12:39 ` Robert Richter
2025-09-12 15:45 ` [PATCH v3 00/11] cxl: ACPI PRM Address Translation Support and AMD Zen5 enablement Dave Jiang
2025-09-15 8:42 ` Robert Richter
2025-09-23 3:26 ` Gregory Price
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