From: Niklas Cassel <cassel@kernel.org>
To: Rob Herring <robh@kernel.org>,
Krzysztof Kozlowski <krzk+dt@kernel.org>,
Conor Dooley <conor+dt@kernel.org>,
Thierry Reding <thierry.reding@gmail.com>,
Jonathan Hunter <jonathanh@nvidia.com>
Cc: Vidya Sagar <vidyas@nvidia.com>,
Shin'ichiro Kawasaki <shinichiro.kawasaki@wdc.com>,
Gautham Srinivasan <gauthams@nvidia.com>,
Niklas Cassel <cassel@kernel.org>,
devicetree@vger.kernel.org, linux-tegra@vger.kernel.org
Subject: [PATCH] arm64: tegra: Add pinctrl definition for PCIe C4 EP
Date: Thu, 18 Sep 2025 14:01:39 +0200 [thread overview]
Message-ID: <20250918120138.17572-2-cassel@kernel.org> (raw)
From: Gautham Srinivasan <gauthams@nvidia.com>
Commit 0580286d0d22 ("arm64: tegra: Add Tegra234 PCIe C4 EP definition")
added the device tree entry "pcie-ep@14160000" for C4 endpoint. However,
it missed pinctrl definition. Without the pinctl definition, the C4
endpoint of Jetson Orin Nano does not work. Add the missing definition.
Signed-off-by: Gautham Srinivasan <gauthams@nvidia.com>
[cassel: add to the existing nodes instead of creating new ones]
Signed-off-by: Niklas Cassel <cassel@kernel.org>
---
arch/arm64/boot/dts/nvidia/tegra234.dtsi | 14 ++++++++++++++
1 file changed, 14 insertions(+)
diff --git a/arch/arm64/boot/dts/nvidia/tegra234.dtsi b/arch/arm64/boot/dts/nvidia/tegra234.dtsi
index df034dbb82853..dd3e51b7d35ef 100644
--- a/arch/arm64/boot/dts/nvidia/tegra234.dtsi
+++ b/arch/arm64/boot/dts/nvidia/tegra234.dtsi
@@ -9,6 +9,7 @@
#include <dt-bindings/power/tegra234-powergate.h>
#include <dt-bindings/reset/tegra234-reset.h>
#include <dt-bindings/thermal/tegra234-bpmp-thermal.h>
+#include <dt-bindings/pinctrl/pinctrl-tegra.h>
/ {
compatible = "nvidia,tegra234";
@@ -127,6 +128,17 @@ gpio: gpio@2200000 {
pinmux: pinmux@2430000 {
compatible = "nvidia,tegra234-pinmux";
reg = <0x0 0x2430000 0x0 0x19100>;
+
+ pex_rst_c4_in_state: pex_rst_c4_in {
+ pex_rst {
+ nvidia,pins = "pex_l4_rst_n_pl1";
+ nvidia,function = "rsvd1";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_ENABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ nvidia,lpdr = <TEGRA_PIN_DISABLE>;
+ };
+ };
};
gpcdma: dma-controller@2600000 {
@@ -4881,6 +4893,8 @@ pcie-ep@14160000 {
<&bpmp TEGRA234_RESET_PEX0_CORE_4>;
reset-names = "apb", "core";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pex_rst_c4_in_state>;
interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>; /* controller interrupt */
interrupt-names = "intr";
nvidia,bpmp = <&bpmp 4>;
--
2.51.0
next reply other threads:[~2025-09-18 12:09 UTC|newest]
Thread overview: 3+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-09-18 12:01 Niklas Cassel [this message]
2025-09-18 14:50 ` [PATCH] arm64: tegra: Add pinctrl definition for PCIe C4 EP Rob Herring (Arm)
-- strict thread matches above, loose matches on Subject: below --
2025-09-19 8:21 kernel test robot
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