From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 88233CAC5B0 for ; Tue, 23 Sep 2025 11:38:21 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:Message-ID:Date:Subject:CC :To:From:Reply-To:Content-ID:Content-Description:Resent-Date:Resent-From: Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:In-Reply-To:References: List-Owner; bh=iXb60Xa4QC0u0xcS1vSakaUOHjW+bMSGycZlyAG3EqU=; b=BeT9K3yZzjXQUz q/mmYm+z4PmBccaqjwD9r9UcefEpXWvzr7Q2RI+m0pHuMBfixSEv4wHcPZ16qcTnXEzV5HcQhcdGG 6MEJjlhLjsv9xJHcztYuVdBs1pIwsjsLqMZ6YtK2rsf5nhPmIcfuIDnpmqDukylRIWeS1iuGc8Afy AsiZqweV3IAzdVt41B5VNna/1NfM1It9DfYgNC8NgeBd7bGPKfIMZLQBJIZ0PcdF9TLmLTEWTRibD wNDQ4JmyCKRHjhKKVOQakMAc6VAFi7wFLdUR7O+J63t67I55AkuAqifVUrEDk3ZeYat/LJ9+L/smb bCPzrOJdq9Qhgy8z1Sxw==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.98.2 #2 (Red Hat Linux)) id 1v11LS-0000000DCEQ-3ce7; Tue, 23 Sep 2025 11:38:06 +0000 Received: from 60-248-80-70.hinet-ip.hinet.net ([60.248.80.70] helo=Atcsqr.andestech.com) by bombadil.infradead.org with esmtps (Exim 4.98.2 #2 (Red Hat Linux)) id 1v11LM-0000000DCBr-3k5B for linux-riscv@lists.infradead.org; Tue, 23 Sep 2025 11:38:03 +0000 Received: from mail.andestech.com (ATCPCS31.andestech.com [10.0.1.89]) by Atcsqr.andestech.com with ESMTPS id 58NBarpR067285 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=OK); Tue, 23 Sep 2025 19:36:53 +0800 (+08) (envelope-from randolph@andestech.com) Received: from atctrx.andestech.com (10.0.15.173) by ATCPCS31.andestech.com (10.0.1.89) with Microsoft SMTP Server id 14.3.498.0; Tue, 23 Sep 2025 19:36:53 +0800 From: Randolph Lin To: CC: , , , , , , , , , , , , , , , , , , , , , , Randolph Lin Subject: [PATCH v3 0/5] Add support for Andes Qilai SoC PCIe controller Date: Tue, 23 Sep 2025 19:36:42 +0800 Message-ID: <20250923113647.895686-1-randolph@andestech.com> X-Mailer: git-send-email 2.34.1 MIME-Version: 1.0 X-Originating-IP: [10.0.15.173] X-DKIM-Results: atcpcs31.andestech.com; dkim=none; X-DNSRBL: X-MAIL: Atcsqr.andestech.com 58NBarpR067285 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20250923_043801_252533_90EC9209 X-CRM114-Status: GOOD ( 11.31 ) X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org Add support for Andes Qilai SoC PCIe controller These patches introduce driver support for the PCIe controller on the Andes Qilai SoC. Signed-off-by: Randolph Lin --- Changes in v3: - Remove outbound ATU address range validation callback and logic. - Add logic to skip failed outbound iATU configuration and continue. - Using PROBE_PREFER_ASYNCHRONOUS as default probe type. - Made minor adjustments based on the reviewer's suggestions. --- Changes in v2: - Remove the patch that adds the dma-ranges property to the SoC node. - Add dma-ranges to the PCIe parent node bus node. - Refactor and rename outbound ATU address range validation callback and logic. - Use parent_bus_offset instead of cpu_addr_fixup(). - Using PROBE_DEFAULT_STRATEGY as default probe type. - Made minor adjustments based on the reviewer's suggestions. Randolph Lin (5): PCI: dwc: Skip failed outbound iATU and continue dt-bindings: PCI: Add Andes QiLai PCIe support riscv: dts: andes: Add PCIe node into the QiLai SoC PCI: andes: Add Andes QiLai SoC PCIe host driver support MAINTAINERS: Add maintainers for Andes QiLai PCIe driver .../bindings/pci/andestech,qilai-pcie.yaml | 102 ++++++++++ MAINTAINERS | 7 + arch/riscv/boot/dts/andes/qilai.dtsi | 109 ++++++++++ drivers/pci/controller/dwc/Kconfig | 13 ++ drivers/pci/controller/dwc/Makefile | 1 + drivers/pci/controller/dwc/pcie-andes-qilai.c | 189 ++++++++++++++++++ .../pci/controller/dwc/pcie-designware-host.c | 9 +- 7 files changed, 426 insertions(+), 4 deletions(-) create mode 100644 Documentation/devicetree/bindings/pci/andestech,qilai-pcie.yaml create mode 100644 drivers/pci/controller/dwc/pcie-andes-qilai.c -- 2.34.1 _______________________________________________ linux-riscv mailing list linux-riscv@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-riscv