[RFC] clk: rockchip: Fix CPLL setup issue

[Alexander Shiyan <eagle.alexander923@gmail.com>]

This is a dirty patch to solve the RK3588 CPLL clock setup issue.
It's taken from the Rockchip U-Boot repository [1].
Any ideas on how to improve it?

[1] https://github.com/rockchip-linux/u-boot/commit/bd11beba4f997b62809d24eba30a8713c8bbeb81

Signed-off-by: Alexander Shiyan <eagle.alexander923@gmail.com>
---
 drivers/clk/rockchip/clk-pll.c | 14 ++++++++++++++
 1 file changed, 14 insertions(+)

diff --git a/drivers/clk/rockchip/clk-pll.c b/drivers/clk/rockchip/clk-pll.c
index 904d70d5d4..4b92639e1b 100644
--- a/drivers/clk/rockchip/clk-pll.c
+++ b/drivers/clk/rockchip/clk-pll.c
@@ -940,6 +940,13 @@ static int rockchip_rk3588_pll_set_params(struct rockchip_clk_pll *pll,
 		}
 	}
 
+	/* Barebox addition */
+	if (pll->reg_base - pll->ctx->reg_base == 0x1a0) {
+		/* Determine CPLL clock and patch clk_bisrintf_pllsrc_en */
+		writel(HIWORD_UPDATE(BIT(1), BIT(1), 0),
+		       pll->ctx->reg_base + 0x84c);
+	}
+
 	/* set pll power down */
 	writel(HIWORD_UPDATE(RK3588_PLLCON1_PWRDOWN,
 			     RK3588_PLLCON1_PWRDOWN, 0),
@@ -971,6 +978,13 @@ static int rockchip_rk3588_pll_set_params(struct rockchip_clk_pll *pll,
 	if ((pll->type == pll_rk3588) && rate_change_remuxed)
 		pll_mux_ops->set_parent(&pll_mux->hw, PLL_MODE_NORM);
 
+	/* Barebox addition */
+	if (pll->reg_base - pll->ctx->reg_base == 0x1a0) {
+		/* Determine CPLL clock and patch clk_bisrintf_pllsrc_en back */
+		writel(HIWORD_UPDATE(0, BIT(1), 0),
+		       pll->ctx->reg_base + 0x84c);
+	}
+
 	return ret;
 }
 
-- 
2.38.2