From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id E6715CAC5B0 for ; Mon, 29 Sep 2025 16:26:48 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1v3Ghd-00028m-OS; Mon, 29 Sep 2025 12:26:20 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1v3GhY-00023x-Ap; Mon, 29 Sep 2025 12:26:13 -0400 Received: from [185.176.79.56] (helo=frasgout.his.huawei.com) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1v3GhR-0008Ow-OO; Mon, 29 Sep 2025 12:26:11 -0400 Received: from mail.maildlp.com (unknown [172.18.186.216]) by frasgout.his.huawei.com (SkyGuard) with ESMTP id 4cb6144y3Kz6M4NR; Tue, 30 Sep 2025 00:22:48 +0800 (CST) Received: from dubpeml100005.china.huawei.com (unknown [7.214.146.113]) by mail.maildlp.com (Postfix) with ESMTPS id 4704A1402F6; Tue, 30 Sep 2025 00:25:54 +0800 (CST) Received: from localhost (10.47.79.72) by dubpeml100005.china.huawei.com (7.214.146.113) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.11; Mon, 29 Sep 2025 17:25:53 +0100 Date: Mon, 29 Sep 2025 17:25:49 +0100 To: Shameer Kolothum CC: , , , , , , , , , , , , , , , , Subject: Re: [PATCH v4 08/27] hw/arm/smmuv3-accel: Add set/unset_iommu_device callback Message-ID: <20250929172549.00005811@huawei.com> In-Reply-To: <20250929133643.38961-9-skolothumtho@nvidia.com> References: <20250929133643.38961-1-skolothumtho@nvidia.com> <20250929133643.38961-9-skolothumtho@nvidia.com> X-Mailer: Claws Mail 4.3.0 (GTK 3.24.42; x86_64-w64-mingw32) MIME-Version: 1.0 Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable X-Originating-IP: [10.47.79.72] X-ClientProxiedBy: lhrpeml100011.china.huawei.com (7.191.174.247) To dubpeml100005.china.huawei.com (7.214.146.113) X-Host-Lookup-Failed: Reverse DNS lookup failed for 185.176.79.56 (deferred) Received-SPF: pass client-ip=185.176.79.56; envelope-from=jonathan.cameron@huawei.com; helo=frasgout.his.huawei.com X-Spam_score_int: -33 X-Spam_score: -3.4 X-Spam_bar: --- X-Spam_report: (-3.4 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_DNSWL_MED=-2.3, RCVD_IN_MSPIKE_H4=0.001, RCVD_IN_MSPIKE_WL=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001, RDNS_NONE=0.793, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Reply-to: Jonathan Cameron From: Jonathan Cameron via Errors-To: qemu-arm-bounces+qemu-arm=archiver.kernel.org@nongnu.org Sender: qemu-arm-bounces+qemu-arm=archiver.kernel.org@nongnu.org On Mon, 29 Sep 2025 14:36:24 +0100 Shameer Kolothum wrote: > From: Nicolin Chen >=20 > Implement a set_iommu_device callback: > -If found an existing viommu reuse that. > -Else, > Allocate a vIOMMU with the nested parent S2 hwpt allocated by VFIO. > Though, iommufd=E2=80=99s vIOMMU model supports nested translation by > encapsulating a S2 nesting parent HWPT, devices cannot attach to this > parent HWPT directly. So two proxy nested HWPTs (bypass and abort) are > allocated to handle device attachments. > -And add the dev to viommu device list >=20 > Also add an unset_iommu_device to unwind/cleanup above. >=20 > Signed-off-by: Nicolin Chen > Signed-off-by: Shameer Kolothum Signed-off-by: Shameer Kolothum Triviality follows. Reviewed-by: Jonathan Cameron > diff --git a/hw/arm/smmuv3-accel.h b/hw/arm/smmuv3-accel.h > index 70da16960f..3c8506d1e6 100644 > --- a/hw/arm/smmuv3-accel.h > +++ b/hw/arm/smmuv3-accel.h > @@ -10,12 +10,29 @@ > #define HW_ARM_SMMUV3_ACCEL_H > =20 > #include "hw/arm/smmu-common.h" > +#include "system/iommufd.h" > +#include > #include CONFIG_DEVICES > =20 > +typedef struct SMMUViommu { > + IOMMUFDBackend *iommufd; > + IOMMUFDViommu core; > + uint32_t bypass_hwpt_id; > + uint32_t abort_hwpt_id; > + QLIST_HEAD(, SMMUv3AccelDevice) device_list; Does that need a forwards def of SMMUv3AccelDevice ? > +} SMMUViommu; > + > typedef struct SMMUv3AccelDevice { > SMMUDevice sdev; I didn't comment on this earlier as thought there would be something added = tht aligned with the above, but seems not. So why the double space? > + HostIOMMUDeviceIOMMUFD *idev; > + SMMUViommu *viommu; > + QLIST_ENTRY(SMMUv3AccelDevice) next; > } SMMUv3AccelDevice; > =20 > +typedef struct SMMUv3AccelState { > + SMMUViommu *viommu; > +} SMMUv3AccelState; > strongarm_uart_update_parameters(const char *label, int speed, char pari= ty, int data_bits, int stop_bits) "%s speed=3D%d parity=3D%c data=3D%d stop= =3D%d" > strongarm_ssp_read_underrun(void) "SSP rx underrun" > diff --git a/include/hw/arm/smmuv3.h b/include/hw/arm/smmuv3.h > index bb7076286b..5f3e9089a7 100644 > --- a/include/hw/arm/smmuv3.h > +++ b/include/hw/arm/smmuv3.h > @@ -66,6 +66,7 @@ struct SMMUv3State { > =20 > /* SMMU has HW accelerator support for nested S1 + s2 */ > bool accel; > + struct SMMUv3AccelState *s_accel; Seems like a bonus space before * > }; > =20 > typedef enum { From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id D6C5CCAC5B9 for ; Mon, 29 Sep 2025 16:27:52 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1v3Ghj-0002EC-4K; Mon, 29 Sep 2025 12:26:23 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1v3GhY-00023x-Ap; Mon, 29 Sep 2025 12:26:13 -0400 Received: from [185.176.79.56] (helo=frasgout.his.huawei.com) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1v3GhR-0008Ow-OO; Mon, 29 Sep 2025 12:26:11 -0400 Received: from mail.maildlp.com (unknown [172.18.186.216]) by frasgout.his.huawei.com (SkyGuard) with ESMTP id 4cb6144y3Kz6M4NR; Tue, 30 Sep 2025 00:22:48 +0800 (CST) Received: from dubpeml100005.china.huawei.com (unknown [7.214.146.113]) by mail.maildlp.com (Postfix) with ESMTPS id 4704A1402F6; Tue, 30 Sep 2025 00:25:54 +0800 (CST) Received: from localhost (10.47.79.72) by dubpeml100005.china.huawei.com (7.214.146.113) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.11; Mon, 29 Sep 2025 17:25:53 +0100 Date: Mon, 29 Sep 2025 17:25:49 +0100 To: Shameer Kolothum CC: , , , , , , , , , , , , , , , , Subject: Re: [PATCH v4 08/27] hw/arm/smmuv3-accel: Add set/unset_iommu_device callback Message-ID: <20250929172549.00005811@huawei.com> In-Reply-To: <20250929133643.38961-9-skolothumtho@nvidia.com> References: <20250929133643.38961-1-skolothumtho@nvidia.com> <20250929133643.38961-9-skolothumtho@nvidia.com> X-Mailer: Claws Mail 4.3.0 (GTK 3.24.42; x86_64-w64-mingw32) MIME-Version: 1.0 Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable X-Originating-IP: [10.47.79.72] X-ClientProxiedBy: lhrpeml100011.china.huawei.com (7.191.174.247) To dubpeml100005.china.huawei.com (7.214.146.113) X-Host-Lookup-Failed: Reverse DNS lookup failed for 185.176.79.56 (deferred) Received-SPF: pass client-ip=185.176.79.56; envelope-from=jonathan.cameron@huawei.com; helo=frasgout.his.huawei.com X-Spam_score_int: -33 X-Spam_score: -3.4 X-Spam_bar: --- X-Spam_report: (-3.4 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_DNSWL_MED=-2.3, RCVD_IN_MSPIKE_H4=0.001, RCVD_IN_MSPIKE_WL=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001, RDNS_NONE=0.793, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Reply-to: Jonathan Cameron From: Jonathan Cameron via Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org On Mon, 29 Sep 2025 14:36:24 +0100 Shameer Kolothum wrote: > From: Nicolin Chen >=20 > Implement a set_iommu_device callback: > -If found an existing viommu reuse that. > -Else, > Allocate a vIOMMU with the nested parent S2 hwpt allocated by VFIO. > Though, iommufd=E2=80=99s vIOMMU model supports nested translation by > encapsulating a S2 nesting parent HWPT, devices cannot attach to this > parent HWPT directly. So two proxy nested HWPTs (bypass and abort) are > allocated to handle device attachments. > -And add the dev to viommu device list >=20 > Also add an unset_iommu_device to unwind/cleanup above. >=20 > Signed-off-by: Nicolin Chen > Signed-off-by: Shameer Kolothum Signed-off-by: Shameer Kolothum Triviality follows. Reviewed-by: Jonathan Cameron > diff --git a/hw/arm/smmuv3-accel.h b/hw/arm/smmuv3-accel.h > index 70da16960f..3c8506d1e6 100644 > --- a/hw/arm/smmuv3-accel.h > +++ b/hw/arm/smmuv3-accel.h > @@ -10,12 +10,29 @@ > #define HW_ARM_SMMUV3_ACCEL_H > =20 > #include "hw/arm/smmu-common.h" > +#include "system/iommufd.h" > +#include > #include CONFIG_DEVICES > =20 > +typedef struct SMMUViommu { > + IOMMUFDBackend *iommufd; > + IOMMUFDViommu core; > + uint32_t bypass_hwpt_id; > + uint32_t abort_hwpt_id; > + QLIST_HEAD(, SMMUv3AccelDevice) device_list; Does that need a forwards def of SMMUv3AccelDevice ? > +} SMMUViommu; > + > typedef struct SMMUv3AccelDevice { > SMMUDevice sdev; I didn't comment on this earlier as thought there would be something added = tht aligned with the above, but seems not. So why the double space? > + HostIOMMUDeviceIOMMUFD *idev; > + SMMUViommu *viommu; > + QLIST_ENTRY(SMMUv3AccelDevice) next; > } SMMUv3AccelDevice; > =20 > +typedef struct SMMUv3AccelState { > + SMMUViommu *viommu; > +} SMMUv3AccelState; > strongarm_uart_update_parameters(const char *label, int speed, char pari= ty, int data_bits, int stop_bits) "%s speed=3D%d parity=3D%c data=3D%d stop= =3D%d" > strongarm_ssp_read_underrun(void) "SSP rx underrun" > diff --git a/include/hw/arm/smmuv3.h b/include/hw/arm/smmuv3.h > index bb7076286b..5f3e9089a7 100644 > --- a/include/hw/arm/smmuv3.h > +++ b/include/hw/arm/smmuv3.h > @@ -66,6 +66,7 @@ struct SMMUv3State { > =20 > /* SMMU has HW accelerator support for nested S1 + s2 */ > bool accel; > + struct SMMUv3AccelState *s_accel; Seems like a bonus space before * > }; > =20 > typedef enum {