Re: [PATCH] cxl/region: Translate DPA->HPA in unaligned MOD3 regions

[Jonathan Cameron <jonathan.cameron@huawei.com>]

On Mon, 29 Sep 2025 21:08:36 -0700
Alison Schofield <alison.schofield@intel.com> wrote:

> The CXL driver implementation of DPA->HPA address translation depends
> on a region's starting address always being aligned to Host Bridge
> Interleave Ways * 256MB. The driver follows the decode methods
> defined in the CXL Spec[1] and expanded upon in the CXL Driver Writers
> Guide[2], which describe bit manipulations based on power-of-2
> alignment to translate a DPA to an HPA.
> 
> With the introduction of MOD3 interleave way support, platforms may
> create regions at starting addresses that are not power-of-2 aligned.
> This allows platforms to avoid gaps in the memory map, but addresses
> within those regions cannot be translated using the existing bit
> manipulation method.
> 
> Introduce an unaligned translation method for DPA->HPA that
> reconstructs an HPA by restoring the address first at the port level
> and then at the host bridge level.
> 
> [1] CXL Spec 3.2 8.2.4.20.13 Implementation Note Device Decoder Logic
> [2] CXL Type 3 Memory Software Guide 1.1 2.13.25 DPA to HPA Translation
> 
> Suggested-by: Qing Huang <qing.huang@intel.com>
> Signed-off-by: Alison Schofield <alison.schofield@intel.com>
Hi Alison,

My 'favourite' headache inducer in the spec. Anyhow, questions on the comments
inline.

J

> ---
> 
> Changes in v1 (was RFC):
> - Replace "/" with do_div() to quiet i386 build warning (lkp)
> - Replace 'cxld->interleave_ways' with 'hbiw' for clarity
> - Use div64_u64_rem() for alignment alignment
> - Fix up a printk format specifier (lkp)
> - Update code comments and commit log
> - Rebase on v717-rc7
> 
>  drivers/cxl/core/region.c | 125 ++++++++++++++++++++++++++++++++++++--
>  1 file changed, 119 insertions(+), 6 deletions(-)
> 
> diff --git a/drivers/cxl/core/region.c b/drivers/cxl/core/region.c
> index 71cc42d05248..4fc0d1450c2c 100644
> --- a/drivers/cxl/core/region.c
> +++ b/drivers/cxl/core/region.c
> @@ -2918,13 +2918,115 @@ static bool cxl_is_hpa_in_chunk(u64 hpa, struct cxl_region *cxlr, int pos)
>  	return false;
>  }
>  
> +static int decode_pos(int region_ways, int pos, int *pos_port, int *pos_hb)
> +{
> +	switch (region_ways) {
> +	/*
> +	 * Extract the port and hb positions from an endpoint position.
> +	 * Knowing there is only one possible decode** for each of these
> +	 * regions, decode logic is:
> +	 *	 3-way: port always 0, hb is pos
> +	 *	 6-way: port cycles thru 0,1, hb increments every 2

Why is 6 host bridge option not relevant?

> +	 *	12-way: port cycles thru 0,1,2,3, hb increments every 4

Why is 6 host bridge option, cycle every 2 or indeed 12 host bridge option
not relevant?

> +	 *
> +	 *	**CXL Spec 3.2 9.13.1.1 Legal Interleaving Configurations
> +	 */
> +	case 3:
> +		*pos_port = 0;
> +		*pos_hb = pos;
> +		break;
> +	case 6:
> +		*pos_port = pos % 2;
> +		*pos_hb = pos / 2;
> +		break;
> +	case 12:
> +		*pos_port = pos % 4;
> +		*pos_hb = pos / 4;
> +		break;
> +	default:
> +		return -EINVAL;
> +	}
> +	return 0;
> +}

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