Re: [PATCH 3/3] PCI: dwc: Enable MSI affinity support

[kernel test robot <lkp@intel.com>]

Hi Radu,

kernel test robot noticed the following build warnings:

[auto build test WARNING on tip/irq/core]
[also build test WARNING on pci/next pci/for-linus mani-mhi/mhi-next linus/master v6.17 next-20251003]
[If your patch is applied to the wrong git tree, kindly drop us a note.
And when submitting patch, we suggest to use '--base' as documented in
https://git-scm.com/docs/git-format-patch#_base_tree_information]

url:    https://github.com/intel-lab-lkp/linux/commits/Radu-Rendec/genirq-Add-interrupt-redirection-infrastructure/20251004-000948
base:   tip/irq/core
patch link:    https://lore.kernel.org/r/20251003160421.951448-4-rrendec%40redhat.com
patch subject: [PATCH 3/3] PCI: dwc: Enable MSI affinity support
config: i386-randconfig-002-20251004 (https://download.01.org/0day-ci/archive/20251004/202510041241.KgbWC5KM-lkp@intel.com/config)
compiler: gcc-14 (Debian 14.2.0-19) 14.2.0
reproduce (this is a W=1 build): (https://download.01.org/0day-ci/archive/20251004/202510041241.KgbWC5KM-lkp@intel.com/reproduce)

If you fix the issue in a separate patch/commit (i.e. not just a new version of
the same patch/commit), kindly add following tags
| Reported-by: kernel test robot <lkp@intel.com>
| Closes: https://lore.kernel.org/oe-kbuild-all/202510041241.KgbWC5KM-lkp@intel.com/

All warnings (new ones prefixed by >>):

>> drivers/pci/controller/dwc/pcie-designware-host.c:137:13: warning: 'dw_pci_pre_redirect' defined but not used [-Wunused-function]
     137 | static void dw_pci_pre_redirect(struct irq_data *d)
         |             ^~~~~~~~~~~~~~~~~~~


vim +/dw_pci_pre_redirect +137 drivers/pci/controller/dwc/pcie-designware-host.c

   136	
 > 137	static void dw_pci_pre_redirect(struct irq_data *d)
   138	{
   139		struct dw_pcie_rp *pp  = irq_data_get_irq_chip_data(d);
   140		struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
   141		unsigned int res, bit, ctrl;
   142	
   143		ctrl = d->hwirq / MAX_MSI_IRQS_PER_CTRL;
   144		res = ctrl * MSI_REG_CTRL_BLOCK_SIZE;
   145		bit = d->hwirq % MAX_MSI_IRQS_PER_CTRL;
   146	
   147		dw_pcie_writel_dbi(pci, PCIE_MSI_INTR0_STATUS + res, BIT(bit));
   148	}
   149	

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