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From: Peter Zijlstra <peterz@infradead.org>
To: Dapeng Mi <dapeng1.mi@linux.intel.com>
Cc: Ingo Molnar <mingo@redhat.com>,
	Arnaldo Carvalho de Melo <acme@kernel.org>,
	Namhyung Kim <namhyung@kernel.org>,
	Ian Rogers <irogers@google.com>,
	Adrian Hunter <adrian.hunter@intel.com>,
	Alexander Shishkin <alexander.shishkin@linux.intel.com>,
	Andi Kleen <ak@linux.intel.com>,
	Eranian Stephane <eranian@google.com>,
	linux-kernel@vger.kernel.org, linux-perf-users@vger.kernel.org,
	Dapeng Mi <dapeng1.mi@intel.com>,
	Kan Liang <kan.liang@linux.intel.com>
Subject: Re: [Patch v8 06/12] perf/x86/intel/ds: Factor out PEBS record processing code to functions
Date: Tue, 21 Oct 2025 17:49:30 +0200	[thread overview]
Message-ID: <20251021154930.GS3245006@noisy.programming.kicks-ass.net> (raw)
In-Reply-To: <20251015064422.47437-7-dapeng1.mi@linux.intel.com>

On Wed, Oct 15, 2025 at 02:44:16PM +0800, Dapeng Mi wrote:

> +static inline void __intel_pmu_handle_pebs_record(struct pt_regs *iregs,
> +						  struct pt_regs *regs,
> +						  struct perf_sample_data *data,
> +						  void *at, u64 pebs_status,
> +						  struct perf_event *events[],
> +						  short *counts, void **last,
> +						  setup_fn setup_sample)
> +{
> +	struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
> +	struct perf_event *event;
> +	int bit;
> +
> +	for_each_set_bit(bit, (unsigned long *)&pebs_status, X86_PMC_IDX_MAX) {
> +		event = cpuc->events[bit];
> +
> +		if (WARN_ON_ONCE(!event) ||
> +		    WARN_ON_ONCE(!event->attr.precise_ip))
> +			continue;
> +
> +		if (counts[bit]++)
> +			__intel_pmu_pebs_event(event, iregs, regs, data,
> +					       last[bit], setup_sample);

No brackets, while coding style requires.

> +
> +		last[bit] = at;
> +		/*
> +		 * perf_event_overflow() called by below __intel_pmu_pebs_last_event()
> +		 * could trigger interrupt throttle and clear all event pointers of
> +		 * the group in cpuc->events[] to NULL. So snapshot the event[] before
> +		 * it could be cleared. This avoids the possible NULL event pointer
> +		 * access and PEBS record loss.
> +		 */
> +		if (counts[bit] && !events[bit])
> +			events[bit] = cpuc->events[bit];
> +	}
> +}


> @@ -2671,41 +2728,15 @@ static void intel_pmu_drain_pebs_icl(struct pt_regs *iregs, struct perf_sample_d
>  		if (basic->format_size != cpuc->pebs_record_size)
>  			continue;
>  
> -		pebs_status = basic->applicable_counters & cpuc->pebs_enabled & mask;
> -		for_each_set_bit(bit, (unsigned long *)&pebs_status, X86_PMC_IDX_MAX) {
> -			event = cpuc->events[bit];
> -
> -			if (WARN_ON_ONCE(!event) ||
> -			    WARN_ON_ONCE(!event->attr.precise_ip))
> -				continue;
> -
> -			if (counts[bit]++) {
> -				__intel_pmu_pebs_event(event, iregs, regs, data, last[bit],
> -						       setup_pebs_adaptive_sample_data);
> -			}

Brackets. Which suggests you took effort to remove them, since cut-paste
code movement would've preserved them.

I've re-instated them.

> -			last[bit] = at;
> -
> -			/*
> -			 * perf_event_overflow() called by below __intel_pmu_pebs_last_event()
> -			 * could trigger interrupt throttle and clear all event pointers of
> -			 * the group in cpuc->events[] to NULL. So snapshot the event[] before
> -			 * it could be cleared. This avoids the possible NULL event pointer
> -			 * access and PEBS record loss.
> -			 */
> -			if (counts[bit] && !events[bit])
> -				events[bit] = cpuc->events[bit];
> -		}
> +		pebs_status = mask & basic->applicable_counters;
> +		__intel_pmu_handle_pebs_record(iregs, regs, data, at,
> +					       pebs_status, events, counts, last,
> +					       setup_pebs_adaptive_sample_data);

  reply	other threads:[~2025-10-21 17:18 UTC|newest]

Thread overview: 22+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2025-10-15  6:44 [Patch v8 00/12] arch-PEBS enabling for Intel platforms Dapeng Mi
2025-10-15  6:44 ` [Patch v8 01/12] perf/x86: Remove redundant is_x86_event() prototype Dapeng Mi
2025-10-15  6:44 ` [Patch v8 02/12] perf/x86/intel: Fix NULL event access and potential PEBS record loss Dapeng Mi
2025-10-22  8:12   ` Mi, Dapeng
2025-10-22 11:24     ` Peter Zijlstra
2025-10-23  2:29       ` Mi, Dapeng
2025-10-15  6:44 ` [Patch v8 03/12] perf/x86/intel: Replace x86_pmu.drain_pebs calling with static call Dapeng Mi
2025-10-15  6:44 ` [Patch v8 04/12] perf/x86/intel: Correct large PEBS flag check Dapeng Mi
2025-10-15  6:44 ` [Patch v8 05/12] perf/x86/intel: Initialize architectural PEBS Dapeng Mi
2025-10-21 15:43   ` Peter Zijlstra
2025-10-22  5:27     ` Mi, Dapeng
2025-10-15  6:44 ` [Patch v8 06/12] perf/x86/intel/ds: Factor out PEBS record processing code to functions Dapeng Mi
2025-10-21 15:49   ` Peter Zijlstra [this message]
2025-10-22  5:32     ` Mi, Dapeng
2025-10-22 11:49   ` Peter Zijlstra
2025-10-23  1:06     ` Mi, Dapeng
2025-10-15  6:44 ` [Patch v8 07/12] perf/x86/intel/ds: Factor out PEBS group " Dapeng Mi
2025-10-15  6:44 ` [Patch v8 08/12] perf/x86/intel: Process arch-PEBS records or record fragments Dapeng Mi
2025-10-15  6:44 ` [Patch v8 09/12] perf/x86/intel: Allocate arch-PEBS buffer and initialize PEBS_BASE MSR Dapeng Mi
2025-10-15  6:44 ` [Patch v8 10/12] perf/x86/intel: Update dyn_constranit base on PEBS event precise level Dapeng Mi
2025-10-15  6:44 ` [Patch v8 11/12] perf/x86/intel: Setup PEBS data configuration and enable legacy groups Dapeng Mi
2025-10-15  6:44 ` [Patch v8 12/12] perf/x86/intel: Add counter group support for arch-PEBS Dapeng Mi

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