From: Jakub Kicinski <kuba@kernel.org>
To: Prabhakar <prabhakar.csengg@gmail.com>
Cc: "Niklas Söderlund" <niklas.soderlund@ragnatech.se>,
"Paul Barker" <paul@pbarker.dev>,
"Andrew Lunn" <andrew+netdev@lunn.ch>,
"David S. Miller" <davem@davemloft.net>,
"Eric Dumazet" <edumazet@google.com>,
"Paolo Abeni" <pabeni@redhat.com>,
"Geert Uytterhoeven" <geert+renesas@glider.be>,
"Mitsuhiro Kimura" <mitsuhiro.kimura.kc@renesas.com>,
netdev@vger.kernel.org, linux-renesas-soc@vger.kernel.org,
linux-kernel@vger.kernel.org,
"Biju Das" <biju.das.jz@bp.renesas.com>,
"Fabrizio Castro" <fabrizio.castro.jz@renesas.com>,
"Lad Prabhakar" <prabhakar.mahadev-lad.rj@bp.renesas.com>,
stable@vger.kernel.org,
"Niklas Söderlund" <niklas.soderlund+renesas@ragnatech.se>
Subject: Re: [PATCH v2 1/4] net: ravb: Make DBAT entry count configurable per-SoC
Date: Wed, 22 Oct 2025 18:13:03 -0700 [thread overview]
Message-ID: <20251022181303.3dc4f41c@kernel.org> (raw)
In-Reply-To: <20251017151830.171062-2-prabhakar.mahadev-lad.rj@bp.renesas.com>
On Fri, 17 Oct 2025 16:18:27 +0100 Prabhakar wrote:
> The number of CDARq (Current Descriptor Address Register) registers is not
> fixed to 22 across all SoC variants. For example, the GBETH implementation
> uses only two entries. Hardcoding the value leads to incorrect resource
> allocation on such platforms.
What is the user-visible problem? "Incorrect resource allocation" could
mean anything from slight waste of system memory to the device falling
over.
If it's the former this is not a fix..
> Pass the DBAT entry count through the per-SoC hardware info struct and use
> it during probe instead of relying on a fixed constant. This ensures
> correct descriptor table sizing and initialization across different SoCs.
>
> Fixes: feab85c7ccea ("ravb: Add support for RZ/G2L SoC")
> Cc: stable@vger.kernel.org
next prev parent reply other threads:[~2025-10-23 1:13 UTC|newest]
Thread overview: 13+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-10-17 15:18 [PATCH v2 0/4] net: ravb: Fix SoC-specific configuration and descriptor handling issues Prabhakar
2025-10-17 15:18 ` [PATCH v2 1/4] net: ravb: Make DBAT entry count configurable per-SoC Prabhakar
2025-10-23 1:13 ` Jakub Kicinski [this message]
2025-10-23 10:51 ` Lad, Prabhakar
2025-10-17 15:18 ` [PATCH v2 2/4] net: ravb: Allocate correct number of queues based on SoC support Prabhakar
2025-10-23 1:13 ` Jakub Kicinski
2025-10-23 10:52 ` Lad, Prabhakar
2025-10-17 15:18 ` [PATCH v2 3/4] net: ravb: Enforce descriptor type ordering Prabhakar
2025-10-22 12:11 ` Niklas Söderlund
2025-10-17 15:18 ` [PATCH v2 4/4] net: ravb: Ensure memory write completes before ringing TX doorbell Prabhakar
2025-10-22 12:16 ` Niklas Söderlund
2025-10-23 1:19 ` [PATCH v2 0/4] net: ravb: Fix SoC-specific configuration and descriptor handling issues Jakub Kicinski
2025-10-23 3:46 ` patchwork-bot+netdevbpf
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