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Thu, 23 Oct 2025 13:21:57 -0700 (PDT) From: Artem Shimko To: Vinod Koul , Eugeniy Paltsev Cc: p.zabel@pengutronix.de, dan.carpenter@linaro.org, a.shimko.dev@gmail.com, linux-kernel@vger.kernel.org, dmaengine@vger.kernel.org Subject: [PATCH v5 3/3] dmaengine: dw-axi-dmac: fix inconsistent indentation in pause/resume functions Date: Thu, 23 Oct 2025 23:21:33 +0300 Message-ID: <20251023202134.1291034-4-a.shimko.dev@gmail.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20251023202134.1291034-1-a.shimko.dev@gmail.com> References: <20251023202134.1291034-1-a.shimko.dev@gmail.com> Precedence: bulk X-Mailing-List: dmaengine@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Fix smatch warnings about inconsistent indentation in dma_chan_pause() and axi_chan_resume() functions. The issue was with misaligned closing braces and incorrect indentation of axi_dma_iowrite64() calls following if-else blocks. The changes address code style violations by correcting misaligned indentation in conditional blocks. Specifically, the closing braces in if-else statements were improperly aligned, and subsequent calls to axi_dma_iowrite64() had incorrect indentation levels. These fixes ensure consistent code formatting according to kernel coding standards while preserving the original functionality and improving overall code readability. Signed-off-by: Artem Shimko --- drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c b/drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c index 1496c52f47a6..7b07bf5ac72b 100644 --- a/drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c +++ b/drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c @@ -1234,7 +1234,7 @@ static int dma_chan_pause(struct dma_chan *dchan) val |= BIT(chan->id) << DMAC_CHAN_SUSP2_SHIFT | BIT(chan->id) << DMAC_CHAN_SUSP2_WE_SHIFT; } - axi_dma_iowrite64(chan->chip, DMAC_CHSUSPREG, val); + axi_dma_iowrite64(chan->chip, DMAC_CHSUSPREG, val); } else { if (chan->chip->dw->hdata->reg_map_8_channels) { val = axi_dma_ioread32(chan->chip, DMAC_CHEN); @@ -1281,7 +1281,7 @@ static inline void axi_chan_resume(struct axi_dma_chan *chan) val &= ~(BIT(chan->id) << DMAC_CHAN_SUSP2_SHIFT); val |= (BIT(chan->id) << DMAC_CHAN_SUSP2_WE_SHIFT); } - axi_dma_iowrite64(chan->chip, DMAC_CHSUSPREG, val); + axi_dma_iowrite64(chan->chip, DMAC_CHSUSPREG, val); } else { if (chan->chip->dw->hdata->reg_map_8_channels) { val = axi_dma_ioread32(chan->chip, DMAC_CHEN); -- 2.43.0