From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from frasgout.his.huawei.com (frasgout.his.huawei.com [185.176.79.56]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 5D3B62DCF70; Fri, 24 Oct 2025 16:25:15 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=185.176.79.56 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1761323120; cv=none; b=VPqpe9W8YZRxjskjl5153bUJi82GfE6ayhuEei4curszpLoPLMyN6OupULgBA+WxAd2WOYPNXGQHBWDVOZpKadYnJibGozskkil9lXf30CXzR80c7EjuvYfHhYL0ggibVz0NOlNCkq45ykOxtt0UXXf6/79ebzBO2lUhmok3keI= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1761323120; c=relaxed/simple; bh=CTvAjivleXHSJk5VwDjixoS2ri9XXj8olENKg9PaxRg=; h=Date:From:To:CC:Subject:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=aC6JphJRHAvWQ5eznIaX3W/wrV2vfMpwr6cQsQ5WXby7xMoE+Nhl9CRx3DTSivGUcqV/DVPD7wJ/46FzSPpgfQsVEU9cPTk6BGObXW6wFXWYWvG730x/kXNbiZlvGRjYMxy0NNF0XNQZVQvN+AAiSXdNjFfxv07fm7N23e8ds9I= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=huawei.com; spf=pass smtp.mailfrom=huawei.com; arc=none smtp.client-ip=185.176.79.56 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=huawei.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=huawei.com Received: from mail.maildlp.com (unknown [172.18.186.231]) by frasgout.his.huawei.com (SkyGuard) with ESMTP id 4ctSpV6KfVz6GDGT; Sat, 25 Oct 2025 00:21:54 +0800 (CST) Received: from dubpeml100005.china.huawei.com (unknown [7.214.146.113]) by mail.maildlp.com (Postfix) with ESMTPS id 934431402ED; Sat, 25 Oct 2025 00:25:13 +0800 (CST) Received: from localhost (10.203.177.15) by dubpeml100005.china.huawei.com (7.214.146.113) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.11; Fri, 24 Oct 2025 17:25:12 +0100 Date: Fri, 24 Oct 2025 17:25:10 +0100 From: Jonathan Cameron To: James Morse CC: , , , D Scott Phillips OS , , , , , , Jamie Iles , Xin Hao , , , , David Hildenbrand , Dave Martin , Koba Ko , Shanker Donthineni , , , Rob Herring , Rohit Mathew , "Rafael Wysocki" , Len Brown , Lorenzo Pieralisi , Hanjun Guo , Sudeep Holla , Catalin Marinas , "Will Deacon" , Greg Kroah-Hartman , Danilo Krummrich , Jeremy Linton , Gavin Shan Subject: Re: [PATCH v3 07/29] arm_mpam: Add probe/remove for mpam msc driver and kbuild boiler plate Message-ID: <20251024172510.0000560b@huawei.com> In-Reply-To: <20251017185645.26604-8-james.morse@arm.com> References: <20251017185645.26604-1-james.morse@arm.com> <20251017185645.26604-8-james.morse@arm.com> X-Mailer: Claws Mail 4.3.0 (GTK 3.24.42; x86_64-w64-mingw32) Precedence: bulk X-Mailing-List: linux-acpi@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="US-ASCII" Content-Transfer-Encoding: 7bit X-ClientProxiedBy: lhrpeml500009.china.huawei.com (7.191.174.84) To dubpeml100005.china.huawei.com (7.214.146.113) On Fri, 17 Oct 2025 18:56:23 +0000 James Morse wrote: > Probing MPAM is convoluted. MSCs that are integrated with a CPU may > only be accessible from those CPUs, and they may not be online. > Touching the hardware early is pointless as MPAM can't be used until > the system-wide common values for num_partid and num_pmg have been > discovered. > > Start with driver probe/remove and mapping the MSC. > > CC: Carl Worth > Tested-by: Fenghua Yu > Signed-off-by: James Morse Trying not to replicate comments too much... A few things inline but others found bigger stuff to fix. > diff --git a/drivers/resctrl/Kconfig b/drivers/resctrl/Kconfig > new file mode 100644 > index 000000000000..58c83b5c8bfd > --- /dev/null > +++ b/drivers/resctrl/Kconfig > @@ -0,0 +1,13 @@ > +menuconfig ARM64_MPAM_DRIVER > + bool "MPAM driver" > + depends on ARM64 && ARM64_MPAM && EXPERT > + help > + MPAM driver for System IP, e,g. caches and memory controllers. Bit minimal for help text :) > + > +if ARM64_MPAM_DRIVER I'd add a blank line here. > +config ARM64_MPAM_DRIVER_DEBUG > + bool "Enable debug messages from the MPAM driver" > + help > + Say yes here to enable debug messages from the MPAM driver. > + > +endif > diff --git a/drivers/resctrl/mpam_devices.c b/drivers/resctrl/mpam_devices.c > new file mode 100644 > index 000000000000..d18eeec95f79 > --- /dev/null > +++ b/drivers/resctrl/mpam_devices.c > +static struct mpam_msc *do_mpam_msc_drv_probe(struct platform_device *pdev) > +{ > + int err; > + u32 tmp; > + struct mpam_msc *msc; > + struct resource *msc_res; > + struct device *dev = &pdev->dev; > + > + lockdep_assert_held(&mpam_list_lock); > + > + msc = devm_kzalloc(&pdev->dev, sizeof(*msc), GFP_KERNEL); > + if (!msc) > + return ERR_PTR(-ENOMEM); > + > + mutex_init(&msc->probe_lock); Maybe worth err = devm_mutex_init(&msc->probe_lock); if (err) return err; to enable the mutex debugging if anyone wants it. I've stopped trying to analyze whether that is useful or not, now it is easy to add to drivers already doing devm. > + mutex_init(&msc->part_sel_lock); > + msc->id = pdev->id; > + msc->pdev = pdev; > + INIT_LIST_HEAD_RCU(&msc->all_msc_list); > + INIT_LIST_HEAD_RCU(&msc->ris); > + > + err = update_msc_accessibility(msc); > + if (err) > + return ERR_PTR(err); > + if (cpumask_empty(&msc->accessibility)) { > + dev_err_once(dev, "MSC is not accessible from any CPU!"); > + return ERR_PTR(-EINVAL); > + } > + > + if (device_property_read_u32(&pdev->dev, "pcc-channel", &tmp)) > + msc->iface = MPAM_IFACE_MMIO; > + else > + msc->iface = MPAM_IFACE_PCC; > + > + if (msc->iface == MPAM_IFACE_MMIO) { > + void __iomem *io; > + > + io = devm_platform_get_and_ioremap_resource(pdev, 0, > + &msc_res); > + if (IS_ERR(io)) { > + dev_err_once(dev, "Failed to map MSC base address\n"); > + return (void *)io; ERR_CAST() is there to make this stuff more obvious > + } > + msc->mapped_hwpage_sz = msc_res->end - msc_res->start; > + msc->mapped_hwpage = io; > + } > + > + list_add_rcu(&msc->all_msc_list, &mpam_all_msc); > + platform_set_drvdata(pdev, msc); > + > + return msc; > +} > + > +static int mpam_msc_drv_probe(struct platform_device *pdev) > +{ > + int err; > + struct mpam_msc *msc = NULL; > + void *plat_data = pdev->dev.platform_data; > + > + mutex_lock(&mpam_list_lock); > + msc = do_mpam_msc_drv_probe(pdev); > + mutex_unlock(&mpam_list_lock); > + if (!IS_ERR(msc)) { > + /* Create RIS entries described by firmware */ > + err = acpi_mpam_parse_resources(msc, plat_data); > + if (err) > + mpam_msc_drv_remove(pdev); > + } else { > + err = PTR_ERR(msc); > + } > + > + if (!err && atomic_add_return(1, &mpam_num_msc) == fw_num_msc) > + pr_info("Discovered all MSC\n"); > + > + return err; > +} > diff --git a/drivers/resctrl/mpam_internal.h b/drivers/resctrl/mpam_internal.h > new file mode 100644 > index 000000000000..6ac75f3613c3 > --- /dev/null > +++ b/drivers/resctrl/mpam_internal.h > @@ -0,0 +1,52 @@ > +/* SPDX-License-Identifier: GPL-2.0 */ > +// Copyright (C) 2025 Arm Ltd. > + > +#ifndef MPAM_INTERNAL_H > +#define MPAM_INTERNAL_H > + > +#include > +#include > +#include > +#include > +#include > +#include > +#include > +#include Includes need another look. Should be seeing the list header for starters and mailbox_client.h doesn't make sense yet. Some of the others may need pushing to the patches where they are first used or pushing down into the c files that need them. > + > +struct platform_device; > + > +struct mpam_msc { > + /* member of mpam_all_msc */ > + struct list_head all_msc_list; > + > + int id; > + struct platform_device *pdev; > + > + /* Not modified after mpam_is_enabled() becomes true */ > + enum mpam_msc_iface iface; > + u32 nrdy_usec; > + cpumask_t accessibility; > + > + /* > + * probe_lock is only taken during discovery. After discovery these > + * properties become read-only and the lists are protected by SRCU. > + */ > + struct mutex probe_lock; > + unsigned long ris_idxs; > + u32 ris_max; > + > + /* mpam_msc_ris of this component */ > + struct list_head ris; > + > + /* > + * part_sel_lock protects access to the MSC hardware registers that are > + * affected by MPAMCFG_PART_SEL. (including the ID registers that vary > + * by RIS). > + * If needed, take msc->probe_lock first. > + */ > + struct mutex part_sel_lock; > + > + void __iomem *mapped_hwpage; > + size_t mapped_hwpage_sz; > +}; > +#endif /* MPAM_INTERNAL_H */