[tip:irq/drivers 23/23] drivers/irqchip/irq-sifive-plic.c:404:17: error: no member named 'enabled_save' in 'struct plic_handler'

[kernel test robot <lkp@intel.com>]

tree:   https://git.kernel.org/pub/scm/linux/kernel/git/tip/tip.git irq/drivers
head:   b5fa8915a50a44c01727ab5b60193188c88e4881
commit: b5fa8915a50a44c01727ab5b60193188c88e4881 [23/23] irqchip/sifive-plic: Add support for UltraRISC DP1000 PLIC
config: riscv-randconfig-002-20251025 (https://download.01.org/0day-ci/archive/20251025/202510250838.m2InkkSl-lkp@intel.com/config)
compiler: clang version 22.0.0git (https://github.com/llvm/llvm-project e1ae12640102fd2b05bc567243580f90acb1135f)
reproduce (this is a W=1 build): (https://download.01.org/0day-ci/archive/20251025/202510250838.m2InkkSl-lkp@intel.com/reproduce)

If you fix the issue in a separate patch/commit (i.e. not just a new version of
the same patch/commit), kindly add following tags
| Reported-by: kernel test robot <lkp@intel.com>
| Closes: https://lore.kernel.org/oe-kbuild-all/202510250838.m2InkkSl-lkp@intel.com/

All errors (new ones prefixed by >>):

>> drivers/irqchip/irq-sifive-plic.c:404:17: error: no member named 'enabled_save' in 'struct plic_handler'
     404 |                 if (!handler->enabled_save[i])
         |                      ~~~~~~~  ^
   drivers/irqchip/irq-sifive-plic.c:407:27: error: no member named 'enabled_save' in 'struct plic_handler'
     407 |                 pending_irqs = handler->enabled_save(i] & readl_relaxed(pending + i);
         |                                ~~~~~~~  ^
   drivers/irqchip/irq-sifive-plic.c:422:28: error: no member named 'enabled_save' in 'struct plic_handler'
     422 |                 if (new_mask != handler->enabled_save[j])
         |                                 ~~~~~~~  ^
   3 errors generated.

Kconfig warnings: (for reference only)
   WARNING: unmet direct dependencies detected for ARCH_HAS_ELF_CORE_EFLAGS
   Depends on [n]: BINFMT_ELF [=y] && ELF_CORE [=n]
   Selected by [y]:
   - RISCV [=y]


vim +404 drivers/irqchip/irq-sifive-plic.c

   393	
   394	static u32 cp100_isolate_pending_irq(int nr_irq_groups, struct plic_handler *handler)
   395	{
   396		u32 __iomem *pending = handler->priv->regs + PENDING_BASE;
   397		u32 __iomem *enable = handler->enable_base;
   398		u32 pending_irqs = 0;
   399		int i, j;
   400	
   401		/* Look for first pending interrupt */
   402		for (i = 0; i < nr_irq_groups; i++) {
   403			/* Any pending interrupts would be annihilated, so skip checking them */
 > 404			if (!handler->enabled_save[i])
   405				continue;
   406	
   407			pending_irqs = handler->enabled_save(i] & readl_relaxed(pending + i);
   408			if (pending_irqs)
   409				break;
   410		}
   411	
   412		if (!pending_irqs)
   413			return 0;
   414	
   415		/* Isolate lowest set bit*/
   416		pending_irqs &= -pending_irqs;
   417	
   418		/* Disable all interrupts but the first pending one */
   419		for (j = 0; j < nr_irq_groups; j++) {
   420			u32 new_mask = j == i ? pending_irqs : 0;
   421	
   422			if (new_mask != handler->enabled_save[j])
   423				writel_relaxed(new_mask, enable + j);
   424		}
   425		return pending_irqs;
   426	}
   427	

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