From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 83157CCD1BF for ; Wed, 29 Oct 2025 04:37:49 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1vDxwB-00071H-Aj; Wed, 29 Oct 2025 00:37:31 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1vDxw7-00070R-Jx; Wed, 29 Oct 2025 00:37:27 -0400 Received: from mail.aspeedtech.com ([211.20.114.72] helo=TWMBX01.aspeed.com) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1vDxw0-0004M3-KA; Wed, 29 Oct 2025 00:37:27 -0400 Received: from TWMBX01.aspeed.com (192.168.0.62) by TWMBX01.aspeed.com (192.168.0.62) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1748.10; Wed, 29 Oct 2025 12:37:10 +0800 Received: from mail.aspeedtech.com (192.168.10.10) by TWMBX01.aspeed.com (192.168.0.62) with Microsoft SMTP Server id 15.2.1748.10 via Frontend Transport; Wed, 29 Oct 2025 12:37:10 +0800 To: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= , Peter Maydell , Steven Lee , Troy Lee , Andrew Jeffery , "Joel Stanley" , "open list:All patches CC here" , "open list:ASPEED BMCs" CC: , , Subject: [PATCH v2 00/17] Split AST2400, AST2600, AST2700 and AST1030 SoC machines into separate source files for maintainability Date: Wed, 29 Oct 2025 12:36:46 +0800 Message-ID: <20251029043710.1486573-1-jamin_lin@aspeedtech.com> X-Mailer: git-send-email 2.43.0 MIME-Version: 1.0 Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=211.20.114.72; envelope-from=jamin_lin@aspeedtech.com; helo=TWMBX01.aspeed.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_VALIDITY_CERTIFIED_BLOCKED=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, SPF_HELO_FAIL=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Reply-to: Jamin Lin From: Jamin Lin via Errors-To: qemu-arm-bounces+qemu-arm=archiver.kernel.org@nongnu.org Sender: qemu-arm-bounces+qemu-arm=archiver.kernel.org@nongnu.org This series depends on the following patch series: Split AST2500 SoC machines into separate source files for maintainability https://patchwork.kernel.org/project/qemu-devel/cover/20251023100150.295370-1-jamin_lin@aspeedtech.com/ v1: 1. Split each Aspeed machine into its own source file for better readability and maintainability: - Quanta-Q71L - Supermicro X11 - Palmetto - Bletchley - fby35 BMC - Facebook Fuji - QCOM Firework - QCOM DC-SCM V1 - GB200NVL - Rainier - Catalina - AST2600 EVB - AST2700 EVB - AST1030 EVB 2. Make aspeed_machine_ast2600_class_emmc_init() a shared API for eMMC boot setup. 3. Promote connect_serial_hds_to_uarts() to a public machine API for reuse across platforms. v2: 1. Restore ASPEED_RAM_SIZE() macro Jamin Lin (17): hw/arm/aspeed: Split Quanta-Q71L machine into a separate source file for maintainability hw/arm/aspeed: Split Supermicro X11 machine into a separate source file for maintainability hw/arm/aspeed: Split Palmetto machine into a separate source file for maintainability hw/arm/aspeed: Move ASPEED_RAM_SIZE() macro to common header for reuse hw/arm/aspeed: Split Bletchley machine into a separate source file for maintainability hw/arm/aspeed: Split FBY35 BMC machine into a separate source file for maintainability hw/arm/aspeed: Split Fuji machine into a separate source file for maintainability hw/arm/aspeed: Split QCOM Firework machine into a separate source file for maintainability hw/arm/aspeed: Split QCOM DC-SCM V1 machine into a separate source file for maintainability hw/arm/aspeed: Make aspeed_machine_ast2600_class_emmc_init() a common API for eMMC boot setup hw/arm/aspeed: Split GB200NVL machine into a separate source file for maintainability hw/arm/aspeed: Split Rainier machine into a separate source file for maintainability hw/arm/aspeed: Split Catalina machine into a separate source file for maintainability hw/arm/aspeed: Split AST2600 EVB machine into a separate source file for maintainability hw/arm/aspeed: Split AST2700 EVB machine into a separate source file for maintainability hw/arm/aspeed: Promote connect_serial_hds_to_uarts() to public machine API hw/arm/aspeed: Split AST1030 EVB machine into a separate source file for maintainability hw/arm/aspeed_eeprom.h | 25 - include/hw/arm/aspeed.h | 9 + hw/arm/aspeed.c | 1144 +---------------- hw/arm/aspeed_ast10x0_evb.c | 107 ++ hw/arm/aspeed_ast2400_palmetto.c | 79 ++ hw/arm/aspeed_ast2400_quanta-q71l.c | 85 ++ hw/arm/aspeed_ast2400_supermicrox11.c | 80 ++ hw/arm/aspeed_ast2600_bletchley.c | 96 ++ hw/arm/aspeed_ast2600_catalina.c | 224 ++++ hw/arm/aspeed_ast2600_evb.c | 64 + ...aspeed_eeprom.c => aspeed_ast2600_fby35.c} | 165 ++- hw/arm/aspeed_ast2600_fuji.c | 139 ++ hw/arm/aspeed_ast2600_gb200nvl.c | 110 ++ hw/arm/aspeed_ast2600_qcom-dc-scm-v1.c | 54 + hw/arm/aspeed_ast2600_qcom-firework.c | 90 ++ hw/arm/aspeed_ast2600_rainier.c | 197 +++ hw/arm/aspeed_ast27x0_evb.c | 86 ++ hw/arm/meson.build | 15 +- 18 files changed, 1533 insertions(+), 1236 deletions(-) delete mode 100644 hw/arm/aspeed_eeprom.h create mode 100644 hw/arm/aspeed_ast10x0_evb.c create mode 100644 hw/arm/aspeed_ast2400_palmetto.c create mode 100644 hw/arm/aspeed_ast2400_quanta-q71l.c create mode 100644 hw/arm/aspeed_ast2400_supermicrox11.c create mode 100644 hw/arm/aspeed_ast2600_bletchley.c create mode 100644 hw/arm/aspeed_ast2600_catalina.c create mode 100644 hw/arm/aspeed_ast2600_evb.c rename hw/arm/{aspeed_eeprom.c => aspeed_ast2600_fby35.c} (51%) create mode 100644 hw/arm/aspeed_ast2600_fuji.c create mode 100644 hw/arm/aspeed_ast2600_gb200nvl.c create mode 100644 hw/arm/aspeed_ast2600_qcom-dc-scm-v1.c create mode 100644 hw/arm/aspeed_ast2600_qcom-firework.c create mode 100644 hw/arm/aspeed_ast2600_rainier.c create mode 100644 hw/arm/aspeed_ast27x0_evb.c -- 2.43.0 From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id E3CA7CCF9E9 for ; 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Wed, 29 Oct 2025 12:37:10 +0800 To: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= , Peter Maydell , Steven Lee , Troy Lee , Andrew Jeffery , "Joel Stanley" , "open list:All patches CC here" , "open list:ASPEED BMCs" CC: , , Subject: [PATCH v2 00/17] Split AST2400, AST2600, AST2700 and AST1030 SoC machines into separate source files for maintainability Date: Wed, 29 Oct 2025 12:36:46 +0800 Message-ID: <20251029043710.1486573-1-jamin_lin@aspeedtech.com> X-Mailer: git-send-email 2.43.0 MIME-Version: 1.0 Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=211.20.114.72; envelope-from=jamin_lin@aspeedtech.com; helo=TWMBX01.aspeed.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_VALIDITY_CERTIFIED_BLOCKED=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, SPF_HELO_FAIL=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Reply-to: Jamin Lin From: Jamin Lin via Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org This series depends on the following patch series: Split AST2500 SoC machines into separate source files for maintainability https://patchwork.kernel.org/project/qemu-devel/cover/20251023100150.295370-1-jamin_lin@aspeedtech.com/ v1: 1. Split each Aspeed machine into its own source file for better readability and maintainability: - Quanta-Q71L - Supermicro X11 - Palmetto - Bletchley - fby35 BMC - Facebook Fuji - QCOM Firework - QCOM DC-SCM V1 - GB200NVL - Rainier - Catalina - AST2600 EVB - AST2700 EVB - AST1030 EVB 2. Make aspeed_machine_ast2600_class_emmc_init() a shared API for eMMC boot setup. 3. Promote connect_serial_hds_to_uarts() to a public machine API for reuse across platforms. v2: 1. Restore ASPEED_RAM_SIZE() macro Jamin Lin (17): hw/arm/aspeed: Split Quanta-Q71L machine into a separate source file for maintainability hw/arm/aspeed: Split Supermicro X11 machine into a separate source file for maintainability hw/arm/aspeed: Split Palmetto machine into a separate source file for maintainability hw/arm/aspeed: Move ASPEED_RAM_SIZE() macro to common header for reuse hw/arm/aspeed: Split Bletchley machine into a separate source file for maintainability hw/arm/aspeed: Split FBY35 BMC machine into a separate source file for maintainability hw/arm/aspeed: Split Fuji machine into a separate source file for maintainability hw/arm/aspeed: Split QCOM Firework machine into a separate source file for maintainability hw/arm/aspeed: Split QCOM DC-SCM V1 machine into a separate source file for maintainability hw/arm/aspeed: Make aspeed_machine_ast2600_class_emmc_init() a common API for eMMC boot setup hw/arm/aspeed: Split GB200NVL machine into a separate source file for maintainability hw/arm/aspeed: Split Rainier machine into a separate source file for maintainability hw/arm/aspeed: Split Catalina machine into a separate source file for maintainability hw/arm/aspeed: Split AST2600 EVB machine into a separate source file for maintainability hw/arm/aspeed: Split AST2700 EVB machine into a separate source file for maintainability hw/arm/aspeed: Promote connect_serial_hds_to_uarts() to public machine API hw/arm/aspeed: Split AST1030 EVB machine into a separate source file for maintainability hw/arm/aspeed_eeprom.h | 25 - include/hw/arm/aspeed.h | 9 + hw/arm/aspeed.c | 1144 +---------------- hw/arm/aspeed_ast10x0_evb.c | 107 ++ hw/arm/aspeed_ast2400_palmetto.c | 79 ++ hw/arm/aspeed_ast2400_quanta-q71l.c | 85 ++ hw/arm/aspeed_ast2400_supermicrox11.c | 80 ++ hw/arm/aspeed_ast2600_bletchley.c | 96 ++ hw/arm/aspeed_ast2600_catalina.c | 224 ++++ hw/arm/aspeed_ast2600_evb.c | 64 + ...aspeed_eeprom.c => aspeed_ast2600_fby35.c} | 165 ++- hw/arm/aspeed_ast2600_fuji.c | 139 ++ hw/arm/aspeed_ast2600_gb200nvl.c | 110 ++ hw/arm/aspeed_ast2600_qcom-dc-scm-v1.c | 54 + hw/arm/aspeed_ast2600_qcom-firework.c | 90 ++ hw/arm/aspeed_ast2600_rainier.c | 197 +++ hw/arm/aspeed_ast27x0_evb.c | 86 ++ hw/arm/meson.build | 15 +- 18 files changed, 1533 insertions(+), 1236 deletions(-) delete mode 100644 hw/arm/aspeed_eeprom.h create mode 100644 hw/arm/aspeed_ast10x0_evb.c create mode 100644 hw/arm/aspeed_ast2400_palmetto.c create mode 100644 hw/arm/aspeed_ast2400_quanta-q71l.c create mode 100644 hw/arm/aspeed_ast2400_supermicrox11.c create mode 100644 hw/arm/aspeed_ast2600_bletchley.c create mode 100644 hw/arm/aspeed_ast2600_catalina.c create mode 100644 hw/arm/aspeed_ast2600_evb.c rename hw/arm/{aspeed_eeprom.c => aspeed_ast2600_fby35.c} (51%) create mode 100644 hw/arm/aspeed_ast2600_fuji.c create mode 100644 hw/arm/aspeed_ast2600_gb200nvl.c create mode 100644 hw/arm/aspeed_ast2600_qcom-dc-scm-v1.c create mode 100644 hw/arm/aspeed_ast2600_qcom-firework.c create mode 100644 hw/arm/aspeed_ast2600_rainier.c create mode 100644 hw/arm/aspeed_ast27x0_evb.c -- 2.43.0