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Tsirkin" To: Sairaj Kodilkar Cc: qemu-devel@nongnu.org, alejandro.j.jimenez@oracle.com, pbonzini@redhat.com, richard.henderson@linaro.org, philmd@linaro.org, suravee.suthikulpanit@amd.com, vasant.hegde@amd.com, marcel.apfelbaum@gmail.com, eduardo@habkost.net, aik@amd.com Subject: Re: [PATCH v3 2/2] amd_iommu: Support 64 bit address for IOTLB lookup Message-ID: <20251103111145-mutt-send-email-mst@kernel.org> References: <20251017061322.1584-1-sarunkod@amd.com> <20251017061322.1584-3-sarunkod@amd.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20251017061322.1584-3-sarunkod@amd.com> Received-SPF: pass client-ip=170.10.133.124; envelope-from=mst@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_VALIDITY_CERTIFIED_BLOCKED=0.001, SPF_HELO_PASS=-0.001, T_SPF_TEMPERROR=0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org On Fri, Oct 17, 2025 at 11:43:22AM +0530, Sairaj Kodilkar wrote: > Physical AMD IOMMU supports up to 64 bits of DMA address. When device tries > to read or write from a given DMA address, IOMMU translates the address > using page table assigned to that device. Since IOMMU uses per device page > tables, the emulated IOMMU should use the cache tag of 68 bits > (64 bit address - 12 bit page alignment + 16 bit device ID). > > Current emulated AMD IOMMU uses GLib hash table to create software iotlb > and uses 64 bit key to store the IOVA and deviceID, which limits the IOVA > to 60 bits. This causes failure while setting up the device when guest is > booted with "iommu.forcedac=1". > > To solve this problem, Use 64 bit IOVA and 16 bit devid as key to store > entries in IOTLB; Use upper 52 bits of IOVA (GFN) and lower 12 bits of > the devid to construct the 64 bit hash key in order avoid the truncation to avoid > as much as possible (reducing hash collisions). > > Fixes: d29a09ca6842 ("hw/i386: Introduce AMD IOMMU") > Signed-off-by: Sairaj Kodilkar > --- > hw/i386/amd_iommu.c | 57 ++++++++++++++++++++++++++++++--------------- > hw/i386/amd_iommu.h | 4 ++-- > 2 files changed, 40 insertions(+), 21 deletions(-) > > diff --git a/hw/i386/amd_iommu.c b/hw/i386/amd_iommu.c > index c2cd5213eb1b..5487894aba40 100644 > --- a/hw/i386/amd_iommu.c > +++ b/hw/i386/amd_iommu.c > @@ -106,6 +106,11 @@ typedef struct AMDVIAsKey { > uint8_t devfn; > } AMDVIAsKey; > > +typedef struct AMDVIIOTLBKey { > + uint64_t gfn; > + uint16_t devid; > +} AMDVIIOTLBKey; > + > uint64_t amdvi_extended_feature_register(AMDVIState *s) > { > uint64_t feature = AMDVI_DEFAULT_EXT_FEATURES; > @@ -377,16 +382,6 @@ static void amdvi_log_pagetab_error(AMDVIState *s, uint16_t devid, > PCI_STATUS_SIG_TARGET_ABORT); > } > > -static gboolean amdvi_uint64_equal(gconstpointer v1, gconstpointer v2) > -{ > - return *((const uint64_t *)v1) == *((const uint64_t *)v2); > -} > - > -static guint amdvi_uint64_hash(gconstpointer v) > -{ > - return (guint)*(const uint64_t *)v; > -} > - > static gboolean amdvi_as_equal(gconstpointer v1, gconstpointer v2) > { > const AMDVIAsKey *key1 = v1; > @@ -425,11 +420,30 @@ static AMDVIAddressSpace *amdvi_get_as_by_devid(AMDVIState *s, uint16_t devid) > amdvi_find_as_by_devid, &devid); > } > > +static gboolean amdvi_iotlb_equal(gconstpointer v1, gconstpointer v2) > +{ > + const AMDVIIOTLBKey *key1 = v1; > + const AMDVIIOTLBKey *key2 = v2; > + > + return key1->devid == key2->devid && key1->gfn == key2->gfn; > +} > + > +static guint amdvi_iotlb_hash(gconstpointer v) > +{ > + const AMDVIIOTLBKey *key = v; > + /* Use GPA and DEVID to find the bucket */ > + return (guint)(key->gfn << AMDVI_PAGE_SHIFT_4K | > + (key->devid & ~AMDVI_PAGE_MASK_4K)); > +} > + > + > static AMDVIIOTLBEntry *amdvi_iotlb_lookup(AMDVIState *s, hwaddr addr, > uint64_t devid) > { > - uint64_t key = (addr >> AMDVI_PAGE_SHIFT_4K) | > - ((uint64_t)(devid) << AMDVI_DEVID_SHIFT); > + AMDVIIOTLBKey key = { > + .gfn = AMDVI_GET_IOTLB_GFN(addr), > + .devid = devid, > + }; > return g_hash_table_lookup(s->iotlb, &key); > } > > @@ -451,8 +465,10 @@ static gboolean amdvi_iotlb_remove_by_devid(gpointer key, gpointer value, > static void amdvi_iotlb_remove_page(AMDVIState *s, hwaddr addr, > uint64_t devid) > { > - uint64_t key = (addr >> AMDVI_PAGE_SHIFT_4K) | > - ((uint64_t)(devid) << AMDVI_DEVID_SHIFT); > + AMDVIIOTLBKey key = { > + .gfn = AMDVI_GET_IOTLB_GFN(addr), > + .devid = devid, > + }; > g_hash_table_remove(s->iotlb, &key); > } > > @@ -463,8 +479,10 @@ static void amdvi_update_iotlb(AMDVIState *s, uint16_t devid, > /* don't cache erroneous translations */ > if (to_cache.perm != IOMMU_NONE) { > AMDVIIOTLBEntry *entry = g_new(AMDVIIOTLBEntry, 1); > - uint64_t *key = g_new(uint64_t, 1); > - uint64_t gfn = gpa >> AMDVI_PAGE_SHIFT_4K; > + AMDVIIOTLBKey *key = g_new(AMDVIIOTLBKey, 1); > + > + key->gfn = AMDVI_GET_IOTLB_GFN(gpa); > + key->devid = devid; > > trace_amdvi_cache_update(domid, PCI_BUS_NUM(devid), PCI_SLOT(devid), > PCI_FUNC(devid), gpa, to_cache.translated_addr); > @@ -477,7 +495,8 @@ static void amdvi_update_iotlb(AMDVIState *s, uint16_t devid, > entry->perms = to_cache.perm; > entry->translated_addr = to_cache.translated_addr; > entry->page_mask = to_cache.addr_mask; > - *key = gfn | ((uint64_t)(devid) << AMDVI_DEVID_SHIFT); > + entry->devid = devid; > + > g_hash_table_replace(s->iotlb, key, entry); > } > } > @@ -2526,8 +2545,8 @@ static void amdvi_sysbus_realize(DeviceState *dev, Error **errp) > } > } > > - s->iotlb = g_hash_table_new_full(amdvi_uint64_hash, > - amdvi_uint64_equal, g_free, g_free); > + s->iotlb = g_hash_table_new_full(amdvi_iotlb_hash, > + amdvi_iotlb_equal, g_free, g_free); > > s->address_spaces = g_hash_table_new_full(amdvi_as_hash, > amdvi_as_equal, g_free, g_free); > diff --git a/hw/i386/amd_iommu.h b/hw/i386/amd_iommu.h > index 38471b95d153..302ccca5121f 100644 > --- a/hw/i386/amd_iommu.h > +++ b/hw/i386/amd_iommu.h > @@ -220,8 +220,8 @@ > #define PAGE_SIZE_PTE_COUNT(pgsz) (1ULL << ((ctz64(pgsz) - 12) % 9)) > > /* IOTLB */ > -#define AMDVI_IOTLB_MAX_SIZE 1024 > -#define AMDVI_DEVID_SHIFT 36 > +#define AMDVI_IOTLB_MAX_SIZE 1024 > +#define AMDVI_GET_IOTLB_GFN(addr) (addr >> AMDVI_PAGE_SHIFT_4K) > > /* default extended feature */ > #define AMDVI_DEFAULT_EXT_FEATURES \ > -- > 2.34.1