From: Bjorn Helgaas <helgaas@kernel.org>
To: Vincent Guittot <vincent.guittot@linaro.org>
Cc: chester62515@gmail.com, mbrugger@suse.com,
ghennadi.procopciuc@oss.nxp.com, s32@nxp.com,
bhelgaas@google.com, jingoohan1@gmail.com, lpieralisi@kernel.org,
kwilczynski@kernel.org, mani@kernel.org, robh@kernel.org,
krzk+dt@kernel.org, conor+dt@kernel.org, Ionut.Vicovan@nxp.com,
larisa.grigore@nxp.com, Ghennadi.Procopciuc@nxp.com,
ciprianmarian.costea@nxp.com, bogdan.hamciuc@nxp.com,
Frank.li@nxp.com, linux-arm-kernel@lists.infradead.org,
linux-pci@vger.kernel.org, devicetree@vger.kernel.org,
linux-kernel@vger.kernel.org, imx@lists.linux.dev,
cassel@kernel.org
Subject: Re: [PATCH 1/4 v3] dt-bindings: PCI: s32g: Add NXP PCIe controller
Date: Wed, 5 Nov 2025 18:00:53 -0600 [thread overview]
Message-ID: <20251106000053.GA1932421@bhelgaas> (raw)
In-Reply-To: <20251022174309.1180931-2-vincent.guittot@linaro.org>
On Wed, Oct 22, 2025 at 07:43:06PM +0200, Vincent Guittot wrote:
> Describe the PCIe host controller available on the S32G platforms.
> + reg = <0x00 0x40400000 0x0 0x00001000>, /* dbi registers */
> + <0x00 0x40420000 0x0 0x00001000>, /* dbi2 registers */
> + <0x00 0x40460000 0x0 0x00001000>, /* atu registers */
> + <0x00 0x40470000 0x0 0x00001000>, /* dma registers */
> + <0x00 0x40481000 0x0 0x000000f8>, /* ctrl registers */
> + <0x5f 0xffffe000 0x0 0x00002000>; /* config space */
Fix comment alignment.
next prev parent reply other threads:[~2025-11-06 0:00 UTC|newest]
Thread overview: 30+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-10-22 17:43 [PATCH 0/4 v3] PCI: s32g: Add support for PCIe controller Vincent Guittot
2025-10-22 17:43 ` [PATCH 1/4 v3] dt-bindings: PCI: s32g: Add NXP " Vincent Guittot
2025-10-22 19:17 ` Frank Li
2025-10-24 6:58 ` Vincent Guittot
2025-11-06 0:00 ` Bjorn Helgaas [this message]
2025-11-06 7:51 ` Vincent Guittot
2025-11-06 7:12 ` Manivannan Sadhasivam
2025-11-06 8:09 ` Vincent Guittot
2025-11-06 17:38 ` Bjorn Helgaas
2025-11-10 9:14 ` Vincent Guittot
2025-10-22 17:43 ` [PATCH 2/4 v3] PCI: dw: Add more registers and bitfield definition Vincent Guittot
2025-10-22 17:43 ` [PATCH 3/4 v3] PCI: s32g: Add initial PCIe support (RC) Vincent Guittot
2025-10-22 19:04 ` Bjorn Helgaas
2025-10-24 6:50 ` Vincent Guittot
2025-11-05 10:28 ` Niklas Cassel
2025-11-05 10:43 ` Ilpo Järvinen
2025-11-05 11:00 ` Niklas Cassel
2025-11-06 0:05 ` Bjorn Helgaas
2025-11-06 6:24 ` Manivannan Sadhasivam
2025-11-06 7:50 ` Vincent Guittot
2025-11-14 10:05 ` Christian Bruel
2025-11-14 21:35 ` Bjorn Helgaas
2025-11-06 7:46 ` Vincent Guittot
2025-10-22 19:44 ` Frank Li
2025-10-24 6:53 ` Vincent Guittot
2025-11-05 7:58 ` Vincent Guittot
2025-11-06 17:23 ` Bjorn Helgaas
2025-11-06 17:33 ` Vincent Guittot
2025-10-22 17:43 ` [PATCH 4/4 v3] MAINTAINERS: Add MAINTAINER for NXP S32G PCIe driver Vincent Guittot
2025-10-22 19:20 ` Frank Li
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