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From: Jason Gunthorpe <jgg@nvidia.com>
To: David Matlack <dmatlack@google.com>
Cc: David Woodhouse <dwmw2@infradead.org>,
	iommu@lists.linux.dev, Joerg Roedel <joro@8bytes.org>,
	Robin Murphy <robin.murphy@arm.com>,
	Will Deacon <will@kernel.org>,
	Lu Baolu <baolu.lu@linux.intel.com>,
	Kevin Tian <kevin.tian@intel.com>,
	patches@lists.linux.dev, Tina Zhang <tina.zhang@intel.com>,
	Wei Wang <wei.w.wang@intel.com>
Subject: Re: [PATCH v3 00/10] Convert Intel VT-d to use the generic iommu page table
Date: Fri, 7 Nov 2025 20:48:19 -0400	[thread overview]
Message-ID: <20251108004819.GD1932966@nvidia.com> (raw)
In-Reply-To: <aQ6OlHhq4TBM6sF8@google.com>

On Sat, Nov 08, 2025 at 12:28:04AM +0000, David Matlack wrote:
> On 2025-10-23 03:22 PM, Jason Gunthorpe wrote:
> > Replace the VT-d iommu_domain implementation of the VT-d second stage and
> > first stage page tables with the iommupt VTDSS and x86_64
> > pagetables. x86_64 is shared with the AMD driver.
> > 
> > VT-d has HW that requires an incoherent page table walker, the majority of
> > the patches are adding generic support for the required cache flushing to
> > iommupt. This is modeled after the existing ARM64 version and is intended
> > to be re-used there.
> > 
> > Applies on top of the AMD conversion:
> >   https://patch.msgid.link/r/0-v2-5c26bde5c22d+58b-iommu_pt_jgg@nvidia.com
> > 
> > This is on github: https://github.com/jgunthorpe/linux/commits/iommu_pt_vtd
> 
> I ran VFIO selftests against this series and did not detect any
> regressions.
> 
> Notably, vfio_dma_mapping_test confirmed that this series did not
> regress VFIO's or IOMMUFD's ability to map 2MB and 1GB HugeTLB pages
> as 2MB and 1GB entries in the I/O page tables as expected.  And
> vfio_pci_driver_test validates that a device (Intel DSA in this case)
> can do DMA, and exercises I/O faulting handling.
> 
> Tested-by: David Matlack <dmatlack@google.com>

Thanks David!

Jason

      reply	other threads:[~2025-11-08  0:48 UTC|newest]

Thread overview: 15+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2025-10-23 18:22 [PATCH v3 00/10] Convert Intel VT-d to use the generic iommu page table Jason Gunthorpe
2025-10-23 18:22 ` [PATCH v3 01/10] iommu/pages: Add support for incoherent IOMMU page table walkers Jason Gunthorpe
2025-10-23 18:22 ` [PATCH v3 02/10] iommupt: Add basic support for SW bits in the page table Jason Gunthorpe
2025-10-28  1:18   ` Tian, Kevin
2025-10-23 18:22 ` [PATCH v3 03/10] iommupt: Use the incoherent start/stop functions for PT_FEAT_DMA_INCOHERENT Jason Gunthorpe
2025-10-23 18:22 ` [PATCH v3 04/10] iommupt: Flush the CPU cache after any writes to the page table Jason Gunthorpe
2025-10-23 18:22 ` [PATCH v3 05/10] iommupt: Add the Intel VT-d second stage page table format Jason Gunthorpe
2025-10-23 18:22 ` [PATCH v3 06/10] iommupt/x86: Set the dirty bit only for writable PTEs Jason Gunthorpe
2025-10-23 18:22 ` [PATCH v3 07/10] iommupt/x86: Support SW bits and permit PT_FEAT_DMA_INCOHERENT Jason Gunthorpe
2025-10-23 18:22 ` [PATCH v3 08/10] iommu/vt-d: Use the generic iommu page table Jason Gunthorpe
2025-10-23 18:22 ` [PATCH v3 09/10] iommu/vt-d: Follow PT_FEAT_DMA_INCOHERENT into the PASID entry Jason Gunthorpe
2025-10-28  1:20   ` Tian, Kevin
2025-10-23 18:22 ` [PATCH v3 10/10] iommupt: Add a kunit test for the SW bits Jason Gunthorpe
2025-11-08  0:28 ` [PATCH v3 00/10] Convert Intel VT-d to use the generic iommu page table David Matlack
2025-11-08  0:48   ` Jason Gunthorpe [this message]

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