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Tue, 11 Nov 2025 15:05:22 -0800 (PST) Received: from localhost ([140.82.166.162]) by smtp.gmail.com with ESMTPSA id e9e14a558f8ab-434733a3854sm3902925ab.34.2025.11.11.15.05.21 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 11 Nov 2025 15:05:21 -0800 (PST) Date: Tue, 11 Nov 2025 17:05:20 -0600 From: Andrew Jones To: Daniel Henrique Barboza Cc: qemu-devel@nongnu.org, qemu-riscv@nongnu.org, alistair.francis@wdc.com, liwei1518@gmail.com, zhiwei_liu@linux.alibaba.com, palmer@dabbelt.com, Fei Wu Subject: Re: [PATCH v4 2/5] target/riscv: Add server platform reference cpu Message-ID: <20251111-e4f4062f326aef78ef820d00@orel> References: <20251111182944.2895892-1-dbarboza@ventanamicro.com> <20251111182944.2895892-3-dbarboza@ventanamicro.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20251111182944.2895892-3-dbarboza@ventanamicro.com> Received-SPF: pass client-ip=2607:f8b0:4864:20::141; envelope-from=ajones@ventanamicro.com; helo=mail-il1-x141.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-riscv@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-riscv-bounces+qemu-riscv=archiver.kernel.org@nongnu.org Sender: qemu-riscv-bounces+qemu-riscv=archiver.kernel.org@nongnu.org On Tue, Nov 11, 2025 at 03:29:41PM -0300, Daniel Henrique Barboza wrote: > From: Fei Wu > > The harts requirements of RISC-V server platform [1] require RVA23 ISA > profile support, plus Sv48, Svadu, H, Sscofmpf etc. > > This patch provides a CPU type (rvsp-ref) to go along with the rvsp-ref > board. > > [1] https://github.com/riscv-non-isa/riscv-server-platform/blob/main/server_platform_requirements.adoc > > Signed-off-by: Fei Wu > Signed-off-by: Daniel Henrique Barboza > --- > target/riscv/cpu-qom.h | 1 + > target/riscv/cpu.c | 14 ++++++++++++++ > 2 files changed, 15 insertions(+) > > diff --git a/target/riscv/cpu-qom.h b/target/riscv/cpu-qom.h > index 75f4e43408..07e96a14ba 100644 > --- a/target/riscv/cpu-qom.h > +++ b/target/riscv/cpu-qom.h > @@ -42,6 +42,7 @@ > #define TYPE_RISCV_CPU_RVA22S64 RISCV_CPU_TYPE_NAME("rva22s64") > #define TYPE_RISCV_CPU_RVA23U64 RISCV_CPU_TYPE_NAME("rva23u64") > #define TYPE_RISCV_CPU_RVA23S64 RISCV_CPU_TYPE_NAME("rva23s64") > +#define TYPE_RISCV_CPU_RVSP_REF RISCV_CPU_TYPE_NAME("rvsp-ref") > #define TYPE_RISCV_CPU_IBEX RISCV_CPU_TYPE_NAME("lowrisc-ibex") > #define TYPE_RISCV_CPU_SHAKTI_C RISCV_CPU_TYPE_NAME("shakti-c") > #define TYPE_RISCV_CPU_SIFIVE_E RISCV_CPU_TYPE_NAME("sifive-e") > diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c > index 975f7953e1..3ddb249970 100644 > --- a/target/riscv/cpu.c > +++ b/target/riscv/cpu.c > @@ -3305,6 +3305,20 @@ static const TypeInfo riscv_cpu_type_infos[] = { > .cfg.max_satp_mode = VM_1_10_SV48, > ), > > + DEFINE_RISCV_CPU(TYPE_RISCV_CPU_RVSP_REF, TYPE_RISCV_BARE_CPU, > + .misa_mxl_max = MXL_RV64, > + .profile = &RVA23S64, > + > + /* > + * ISA extensions > + * NOTE: we're missing 'sdext'. > + */ > + .cfg.ext_zkr = true, > + .cfg.ext_svadu = true, Svadu is no longer required. > + > + .cfg.max_satp_mode = VM_1_10_SV57, Shouldn't this be SV48 and then allow instantiations to use rvsp-ref,sv57=on. We also need Ssccfg and Sdtrig. > + ), > + > #if defined(CONFIG_TCG) && !defined(CONFIG_USER_ONLY) > DEFINE_RISCV_CPU(TYPE_RISCV_CPU_BASE128, TYPE_RISCV_DYNAMIC_CPU, > .cfg.max_satp_mode = VM_1_10_SV57, > -- > 2.51.1 > > Thanks, drew