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Tue, 11 Nov 2025 10:30:03 -0800 (PST) Received: from grind.dc1.ventanamicro.com ([179.93.21.233]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-3434c2ffdecsm15207419a91.2.2025.11.11.10.29.57 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 11 Nov 2025 10:30:03 -0800 (PST) From: Daniel Henrique Barboza To: qemu-devel@nongnu.org Cc: qemu-riscv@nongnu.org, alistair.francis@wdc.com, liwei1518@gmail.com, zhiwei_liu@linux.alibaba.com, palmer@dabbelt.com, Daniel Henrique Barboza , Andrew Jones Subject: [PATCH v4 1/5] target/riscv/cpu.c: remove 'bare' condition for .profile Date: Tue, 11 Nov 2025 15:29:40 -0300 Message-ID: <20251111182944.2895892-2-dbarboza@ventanamicro.com> X-Mailer: git-send-email 2.51.1 In-Reply-To: <20251111182944.2895892-1-dbarboza@ventanamicro.com> References: <20251111182944.2895892-1-dbarboza@ventanamicro.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2607:f8b0:4864:20::1035; envelope-from=dbarboza@ventanamicro.com; helo=mail-pj1-x1035.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-riscv@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-riscv-bounces+qemu-riscv=archiver.kernel.org@nongnu.org Sender: qemu-riscv-bounces+qemu-riscv=archiver.kernel.org@nongnu.org We want to configure other CPU types to use profiles as an alternative to adding every profile extension explicitly, i.e. a profile is nothing more than an extension bundle. This means that a vendor CPU can set .profile=rva23s64 while having the same handling as any other vendor CPU. Same thing with all other CPU types. Signed-off-by: Daniel Henrique Barboza Reviewed-by: Andrew Jones --- target/riscv/cpu.c | 1 - 1 file changed, 1 deletion(-) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 73d4280d7c..975f7953e1 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -2792,7 +2792,6 @@ static void riscv_cpu_class_base_init(ObjectClass *c, const void *data) mcc->def->bare |= def->bare; if (def->profile) { assert(profile_extends(def->profile, mcc->def->profile)); - assert(mcc->def->bare); mcc->def->profile = def->profile; } if (def->misa_mxl_max) { -- 2.51.1