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From: Jonathan Cameron <jonathan.cameron@huawei.com>
To: <alejandro.lucero-palau@amd.com>
Cc: <linux-cxl@vger.kernel.org>, <netdev@vger.kernel.org>,
	<dan.j.williams@intel.com>, <edward.cree@amd.com>,
	<davem@davemloft.net>, <kuba@kernel.org>, <pabeni@redhat.com>,
	<edumazet@google.com>, <dave.jiang@intel.com>,
	Alejandro Lucero <alucerop@amd.com>,
	"Alison Schofield" <alison.schofield@intel.com>,
	Ben Cheatham <benjamin.cheatham@amd.com>
Subject: Re: [PATCH v20 04/22] cxl: Add type2 device basic support
Date: Wed, 12 Nov 2025 15:33:34 +0000	[thread overview]
Message-ID: <20251112153334.00000ea2@huawei.com> (raw)
In-Reply-To: <20251110153657.2706192-5-alejandro.lucero-palau@amd.com>

On Mon, 10 Nov 2025 15:36:39 +0000
alejandro.lucero-palau@amd.com wrote:

> From: Alejandro Lucero <alucerop@amd.com>
> 
> Differentiate CXL memory expanders (type 3) from CXL device accelerators
> (type 2) with a new function for initializing cxl_dev_state and a macro
> for helping accel drivers to embed cxl_dev_state inside a private
> struct.
> 
> Move structs to include/cxl as the size of the accel driver private
> struct embedding cxl_dev_state needs to know the size of this struct.
> 
> Use same new initialization with the type3 pci driver.
> 
> Signed-off-by: Alejandro Lucero <alucerop@amd.com>
> Reviewed-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
> Reviewed-by: Dave Jiang <dave.jiang@intel.com>
> Reviewed-by: Alison Schofield <alison.schofield@intel.com>
> Reviewed-by: Ben Cheatham <benjamin.cheatham@amd.com>
One minor thing that's probably a merge conflict gone slightly wrong
or something like that. After this patch you end up with two
CXL_NR_PARTITIONS_MAX defines.

> ---
>  drivers/cxl/core/mbox.c      |  12 +-
>  drivers/cxl/core/memdev.c    |  32 +++++
>  drivers/cxl/core/pci_drv.c   |  15 +--
>  drivers/cxl/cxl.h            |  97 +--------------
>  drivers/cxl/cxlmem.h         |  85 +------------
>  include/cxl/cxl.h            | 226 +++++++++++++++++++++++++++++++++++
>  tools/testing/cxl/test/mem.c |   3 +-
>  7 files changed, 276 insertions(+), 194 deletions(-)
>  create mode 100644 include/cxl/cxl.h
> 

> diff --git a/include/cxl/cxl.h b/include/cxl/cxl.h
> new file mode 100644
> index 000000000000..13d448686189
> --- /dev/null
> +++ b/include/cxl/cxl.h
> @@ -0,0 +1,226 @@



> +#define CXL_NR_PARTITIONS_MAX 2
Adds a definition but doesn't remove the one in driver/cxl/cxlmem.h
That seems odd.




  reply	other threads:[~2025-11-12 15:33 UTC|newest]

Thread overview: 54+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2025-11-10 15:36 [PATCH v20 00/22] Type2 device basic support alejandro.lucero-palau
2025-11-10 15:36 ` [PATCH v20 01/22] cxl/mem: Arrange for always-synchronous memdev attach alejandro.lucero-palau
2025-11-12 14:53   ` Jonathan Cameron
2025-11-14 11:10     ` Alejandro Lucero Palau
2025-11-14 15:24       ` Dave Jiang
2025-11-10 15:36 ` [PATCH v20 02/22] cxl/port: Arrange for always synchronous endpoint attach alejandro.lucero-palau
2025-11-12 14:57   ` Jonathan Cameron
2025-11-13 23:01   ` Dave Jiang
2025-11-10 15:36 ` [PATCH v20 03/22] cxl/mem: Introduce a memdev creation ->probe() operation alejandro.lucero-palau
2025-11-12 15:00   ` Jonathan Cameron
2025-11-13 23:02   ` Dave Jiang
2025-11-10 15:36 ` [PATCH v20 04/22] cxl: Add type2 device basic support alejandro.lucero-palau
2025-11-12 15:33   ` Jonathan Cameron [this message]
2025-11-15  8:11     ` Alejandro Lucero Palau
2025-11-10 15:36 ` [PATCH v20 05/22] sfc: add cxl support alejandro.lucero-palau
2025-11-10 15:36 ` [PATCH v20 06/22] cxl: Move pci generic code alejandro.lucero-palau
2025-11-12 15:41   ` Jonathan Cameron
2025-11-15  8:12     ` Alejandro Lucero Palau
2025-11-17 15:00       ` Dave Jiang
2025-11-18 14:52         ` Alejandro Lucero Palau
2025-11-14  0:25   ` Alison Schofield
2025-11-14 16:15     ` Dave Jiang
2025-11-15  8:16     ` Alejandro Lucero Palau
2025-11-16  2:07       ` Alison Schofield
2025-11-18 14:55         ` Alejandro Lucero Palau
2025-11-10 15:36 ` [PATCH v20 07/22] cxl/sfc: Map cxl component regs alejandro.lucero-palau
2025-11-12 15:45   ` Jonathan Cameron
2025-11-12 15:52     ` Jonathan Cameron
2025-11-10 15:36 ` [PATCH v20 08/22] cxl/sfc: Initialize dpa without a mailbox alejandro.lucero-palau
2025-11-12 15:52   ` Jonathan Cameron
2025-11-10 15:36 ` [PATCH v20 09/22] cxl: Prepare memdev creation for type2 alejandro.lucero-palau
2025-11-10 15:36 ` [PATCH v20 10/22] sfc: create type2 cxl memdev alejandro.lucero-palau
2025-11-10 15:36 ` [PATCH v20 11/22] cxl: Define a driver interface for HPA free space enumeration alejandro.lucero-palau
2025-11-12 16:10   ` Jonathan Cameron
2025-11-19 17:16     ` Alejandro Lucero Palau
2025-11-10 15:36 ` [PATCH v20 12/22] sfc: get root decoder alejandro.lucero-palau
2025-11-10 15:36 ` [PATCH v20 13/22] cxl: Define a driver interface for DPA allocation alejandro.lucero-palau
2025-11-10 15:36 ` [PATCH v20 14/22] sfc: get endpoint decoder alejandro.lucero-palau
2025-11-13 23:52   ` Dave Jiang
2025-11-10 15:36 ` [PATCH v20 15/22] cxl: Make region type based on endpoint type alejandro.lucero-palau
2025-11-10 15:36 ` [PATCH v20 16/22] cxl/region: Factor out interleave ways setup alejandro.lucero-palau
2025-11-10 15:36 ` [PATCH v20 17/22] cxl/region: Factor out interleave granularity setup alejandro.lucero-palau
2025-11-10 15:36 ` [PATCH v20 18/22] cxl: Allow region creation by type2 drivers alejandro.lucero-palau
2025-11-12 16:19   ` Jonathan Cameron
2025-11-19 18:31     ` Alejandro Lucero Palau
2025-11-14  0:00   ` Dave Jiang
2025-11-10 15:36 ` [PATCH v20 19/22] cxl: Avoid dax creation for accelerators alejandro.lucero-palau
2025-11-10 15:36 ` [PATCH v20 20/22] sfc: create cxl region alejandro.lucero-palau
2025-11-12 16:21   ` Jonathan Cameron
2025-11-14  0:02   ` Dave Jiang
2025-11-10 15:36 ` [PATCH v20 21/22] cxl: Add function for obtaining region range alejandro.lucero-palau
2025-11-10 15:36 ` [PATCH v20 22/22] sfc: support pio mapping based on cxl alejandro.lucero-palau
2025-11-12 16:24   ` Jonathan Cameron
2025-11-14  0:03   ` Dave Jiang

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