From: Borislav Petkov <bp@alien8.de>
To: Avadhut Naik <avadhut.naik@amd.com>
Cc: x86@kernel.org, linux-edac@vger.kernel.org, tony.luck@intel.com,
yazen.ghannam@amd.com, linux-kernel@vger.kernel.org
Subject: Re: [PATCH v2] x86/mce: Add support for PHYSADDRV and PHYSADDRVALIDSUPPORTED bits
Date: Thu, 13 Nov 2025 17:52:56 +0100 [thread overview]
Message-ID: <20251113165256.GEaRYM6KyP299yO2Pi@fat_crate.local> (raw)
In-Reply-To: <20251015172452.3649720-1-avadhut.naik@amd.com>
On Wed, Oct 15, 2025 at 05:22:25PM +0000, Avadhut Naik wrote:
> @@ -777,6 +781,11 @@ bool amd_mce_usable_address(struct mce *m)
> return false;
> }
>
> + rdmsrl(MSR_AMD64_SMCA_MCx_CONFIG(m->bank), smca_config);
We have struct smca_bank and per-CPU smca_banks array.
MCI_CONFIG_PADDRV looks like a property of the bank which is static and
doesn't change willy-nilly. So instead of doing the silly MSR read on every
error, you can cache the fact that the bank supports MCI_STATUS_PADDRV and
query that and save us 100+ unnecessary cycles every time...
No?
Thx.
--
Regards/Gruss,
Boris.
https://people.kernel.org/tglx/notes-about-netiquette
next prev parent reply other threads:[~2025-11-13 16:53 UTC|newest]
Thread overview: 6+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-10-15 17:22 [PATCH v2] x86/mce: Add support for PHYSADDRV and PHYSADDRVALIDSUPPORTED bits Avadhut Naik
2025-10-17 14:31 ` Yazen Ghannam
2025-10-17 16:44 ` Naik, Avadhut
2025-11-13 16:52 ` Borislav Petkov [this message]
2025-11-14 20:20 ` [PATCH] " Avadhut Naik
2025-11-16 18:05 ` Borislav Petkov
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