From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 1056FCDE002 for ; Fri, 14 Nov 2025 03:53:52 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 6C4D810E99C; Fri, 14 Nov 2025 03:53:51 +0000 (UTC) Received: from us-smtp-delivery-44.mimecast.com (us-smtp-delivery-44.mimecast.com [205.139.111.44]) by gabe.freedesktop.org (Postfix) with ESMTPS id 625FB10E99C for ; Fri, 14 Nov 2025 03:53:49 +0000 (UTC) Received: from mx-prod-mc-03.mail-002.prod.us-west-2.aws.redhat.com (ec2-54-186-198-63.us-west-2.compute.amazonaws.com [54.186.198.63]) by relay.mimecast.com with ESMTP with STARTTLS (version=TLSv1.3, cipher=TLS_AES_256_GCM_SHA384) id us-mta-306-OlcnbYsgMruUKfdHCX-YdA-1; Thu, 13 Nov 2025 22:53:46 -0500 X-MC-Unique: OlcnbYsgMruUKfdHCX-YdA-1 X-Mimecast-MFC-AGG-ID: OlcnbYsgMruUKfdHCX-YdA_1763092425 Received: from mx-prod-int-03.mail-002.prod.us-west-2.aws.redhat.com (mx-prod-int-03.mail-002.prod.us-west-2.aws.redhat.com [10.30.177.12]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (2048 bits) server-digest SHA256) (No client certificate requested) by mx-prod-mc-03.mail-002.prod.us-west-2.aws.redhat.com (Postfix) with ESMTPS id 0BAB919560B2 for ; Fri, 14 Nov 2025 03:53:45 +0000 (UTC) Received: from dreadlord.redhat.com (unknown [10.67.32.53]) by mx-prod-int-03.mail-002.prod.us-west-2.aws.redhat.com (Postfix) with ESMTP id 972BC19560B9 for ; Fri, 14 Nov 2025 03:53:43 +0000 (UTC) From: Dave Airlie To: dri-devel@lists.freedesktop.org Subject: [PATCH 2/2] amd/dc: add frl bits to the registers Date: Fri, 14 Nov 2025 13:53:38 +1000 Message-ID: <20251114035338.15144-2-airlied@gmail.com> In-Reply-To: <20251114035338.15144-1-airlied@gmail.com> References: <20251114035338.15144-1-airlied@gmail.com> MIME-Version: 1.0 X-Scanned-By: MIMEDefang 3.0 on 10.30.177.12 X-Mimecast-Spam-Score: 0 X-Mimecast-MFC-PROC-ID: ud9Gf-naUceD_Q1d6YDNovNjT3f80ncXkMYNDQjcfJY_1763092425 X-Mimecast-Originator: gmail.com Content-Transfer-Encoding: quoted-printable content-type: text/plain; charset=WINDOWS-1252; x-default=true X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" From: Dave Airlie document the same bits as added to the main headers. Signed-off-by: Dave Airlie --- .../gpu/drm/amd/display/dc/dc_hdmi_types.h | 30 +++++++++++++++++-- 1 file changed, 28 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/amd/display/dc/dc_hdmi_types.h b/drivers/gpu/d= rm/amd/display/dc/dc_hdmi_types.h index b015e80672ec..693129b987ac 100644 --- a/drivers/gpu/drm/amd/display/dc/dc_hdmi_types.h +++ b/drivers/gpu/drm/amd/display/dc/dc_hdmi_types.h @@ -77,11 +77,24 @@ union hdmi_scdc_update_read_data { =09=09uint8_t STATUS_UPDATE:1; =09=09uint8_t CED_UPDATE:1; =09=09uint8_t RR_TEST:1; -=09=09uint8_t RESERVED:5; +=09=09uint8_t RESERVED0:1; +=09=09uint8_t FRL_START:1; +=09=09uint8_t FLT_UPDATE:1; +=09=09uint8_t RESERVED:2; =09=09uint8_t RESERVED2:8; =09} fields; }; =20 +union hdmi_scdc_config_data { +=09uint8_t byte[2]; +=09struct { +=09=09uint8_t RR_ENABLE:1; +=09=09uint8_t RESERVED:7; +=09=09uint8_t FRL_RATE:4; +=09=09uint8_t FFE_LEVELS:4; +=09} fields; +}; + union hdmi_scdc_status_flags_data { =09uint8_t byte; =09struct { @@ -89,7 +102,20 @@ union hdmi_scdc_status_flags_data { =09=09uint8_t CH0_LOCKED:1; =09=09uint8_t CH1_LOCKED:1; =09=09uint8_t CH2_LOCKED:1; -=09=09uint8_t RESERVED:4; +=09=09uint8_t LANE3_LOCKED:1; +=09=09uint8_t RESERVED:1; +=09=09uint8_t FLT_READY:1; +=09=09uint8_t RESERVED2:1; +=09} fields; +}; + +union hdmi_scdc_lane_status_data { +=09uint8_t byte[2]; +=09struct { +=09=09uint8_t ltp_0:4; +=09=09uint8_t ltp_1:4; +=09=09uint8_t ltp_2:4; +=09=09uint8_t ltp_3:4; =09} fields; }; =20 --=20 2.51.1