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CTRY:US; LANG:en; SCL:1; SRV:; IPV:NLI; SFV:NSPM; H:satlexmb07.amd.com; PTR:InfoDomainNonexistent; CAT:NONE; SFS:(13230040)(82310400026)(376014)(36860700013)(1800799024); DIR:OUT; SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 18 Nov 2025 08:24:56.4168 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: e96556bf-1a2a-4632-a0b0-08de267bf4ea X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d; Ip=[165.204.84.17]; Helo=[satlexmb07.amd.com] X-MS-Exchange-CrossTenant-AuthSource: CY4PEPF0000E9D4.namprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: MN2PR12MB4342 Received-SPF: permerror client-ip=2a01:111:f403:c107::9; envelope-from=Sairaj.ArunKodilkar@amd.com; helo=PH7PR06CU001.outbound.protection.outlook.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Current code uses 32 bit cpu destination irrespective of the fact that guest has enabled xt support through control register[XTEn] and completely depends on command line parameter xtsup=on. This is not a correct hardware behaviour and can cause problems in the guest which has not enabled XT mode. Introduce new flag "xten", which is enabled when guest writes 1 to the control register bit 50 (XTEn). Signed-off-by: Sairaj Kodilkar --- hw/i386/amd_iommu.c | 3 ++- hw/i386/amd_iommu.h | 4 +++- 2 files changed, 5 insertions(+), 2 deletions(-) diff --git a/hw/i386/amd_iommu.c b/hw/i386/amd_iommu.c index a9ee7150ef17..7f08fc31111a 100644 --- a/hw/i386/amd_iommu.c +++ b/hw/i386/amd_iommu.c @@ -1548,6 +1548,7 @@ static void amdvi_handle_control_write(AMDVIState *s) s->cmdbuf_enabled = s->enabled && !!(control & AMDVI_MMIO_CONTROL_CMDBUFLEN); s->ga_enabled = !!(control & AMDVI_MMIO_CONTROL_GAEN); + s->xten = !!(control & AMDVI_MMIO_CONTROL_XTEN) && s->xtsup; /* update the flags depending on the control register */ if (s->cmdbuf_enabled) { @@ -2020,7 +2021,7 @@ static int amdvi_int_remap_ga(AMDVIState *iommu, irq->vector = irte.hi.fields.vector; irq->dest_mode = irte.lo.fields_remap.dm; irq->redir_hint = irte.lo.fields_remap.rq_eoi; - if (iommu->xtsup) { + if (iommu->xten) { irq->dest = irte.lo.fields_remap.destination | (irte.hi.fields.destination_hi << 24); } else { diff --git a/hw/i386/amd_iommu.h b/hw/i386/amd_iommu.h index 302ccca5121f..32467d0bc241 100644 --- a/hw/i386/amd_iommu.h +++ b/hw/i386/amd_iommu.h @@ -106,6 +106,7 @@ #define AMDVI_MMIO_CONTROL_COMWAITINTEN (1ULL << 4) #define AMDVI_MMIO_CONTROL_CMDBUFLEN (1ULL << 12) #define AMDVI_MMIO_CONTROL_GAEN (1ULL << 17) +#define AMDVI_MMIO_CONTROL_XTEN (1ULL << 50) /* MMIO status register bits */ #define AMDVI_MMIO_STATUS_CMDBUF_RUN (1 << 4) @@ -418,7 +419,8 @@ struct AMDVIState { /* Interrupt remapping */ bool ga_enabled; - bool xtsup; + bool xtsup; /* xtsup=on command line */ + bool xten; /* Enable x2apic */ /* DMA address translation */ bool dma_remap; -- 2.34.1