From: kernel test robot <lkp@intel.com>
To: Prabhakar <prabhakar.csengg@gmail.com>,
Geert Uytterhoeven <geert+renesas@glider.be>,
Michael Turquette <mturquette@baylibre.com>,
Stephen Boyd <sboyd@kernel.org>
Cc: oe-kbuild-all@lists.linux.dev, linux-renesas-soc@vger.kernel.org,
linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org,
Prabhakar <prabhakar.csengg@gmail.com>,
Biju Das <biju.das.jz@bp.renesas.com>,
Fabrizio Castro <fabrizio.castro.jz@renesas.com>,
Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Subject: Re: [PATCH v3] clk: renesas: r9a09g077: Add xSPI core and module clocks
Date: Tue, 18 Nov 2025 18:00:58 +0800 [thread overview]
Message-ID: <202511181758.cZTukDMh-lkp@intel.com> (raw)
In-Reply-To: <20251117205627.39376-1-prabhakar.mahadev-lad.rj@bp.renesas.com>
Hi Prabhakar,
kernel test robot noticed the following build errors:
[auto build test ERROR on geert-renesas-drivers/renesas-clk]
[also build test ERROR on next-20251118]
[cannot apply to clk/clk-next linus/master v6.18-rc6]
[If your patch is applied to the wrong git tree, kindly drop us a note.
And when submitting patch, we suggest to use '--base' as documented in
https://git-scm.com/docs/git-format-patch#_base_tree_information]
url: https://github.com/intel-lab-lkp/linux/commits/Prabhakar/clk-renesas-r9a09g077-Add-xSPI-core-and-module-clocks/20251118-045831
base: https://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers.git renesas-clk
patch link: https://lore.kernel.org/r/20251117205627.39376-1-prabhakar.mahadev-lad.rj%40bp.renesas.com
patch subject: [PATCH v3] clk: renesas: r9a09g077: Add xSPI core and module clocks
config: arm-randconfig-001-20251118 (https://download.01.org/0day-ci/archive/20251118/202511181758.cZTukDMh-lkp@intel.com/config)
compiler: arm-linux-gnueabi-gcc (GCC) 8.5.0
reproduce (this is a W=1 build): (https://download.01.org/0day-ci/archive/20251118/202511181758.cZTukDMh-lkp@intel.com/reproduce)
If you fix the issue in a separate patch/commit (i.e. not just a new version of
the same patch/commit), kindly add following tags
| Reported-by: kernel test robot <lkp@intel.com>
| Closes: https://lore.kernel.org/oe-kbuild-all/202511181758.cZTukDMh-lkp@intel.com/
All errors (new ones prefixed by >>):
>> drivers/clk/renesas/r9a09g077-cpg.c:88:21: error: 'R9A09G077_XSPI_CLK1' undeclared here (not in a function); did you mean 'R9A09G077_USB_CLK'?
LAST_DT_CORE_CLK = R9A09G077_XSPI_CLK1,
^~~~~~~~~~~~~~~~~~~
R9A09G077_USB_CLK
In file included from drivers/clk/renesas/r9a09g077-cpg.c:19:
>> drivers/clk/renesas/r9a09g077-cpg.c:230:32: error: 'R9A09G077_XSPI_CLK0' undeclared here (not in a function); did you mean 'R9A09G077_USB_CLK'?
DEF_DIV_FSELXSPI("XSPI_CLK0", R9A09G077_XSPI_CLK0, CLK_DIVSELXSPI0_SCKCR,
^~~~~~~~~~~~~~~~~~~
drivers/clk/renesas/renesas-cpg-mssr.h:72:25: note: in definition of macro 'DEF_TYPE'
{ .name = _name, .id = _id, .type = _type }
^~~
drivers/clk/renesas/r9a09g077-cpg.c:230:2: note: in expansion of macro 'DEF_DIV_FSELXSPI'
DEF_DIV_FSELXSPI("XSPI_CLK0", R9A09G077_XSPI_CLK0, CLK_DIVSELXSPI0_SCKCR,
^~~~~~~~~~~~~~~~
vim +88 drivers/clk/renesas/r9a09g077-cpg.c
74
75 #define DEF_DIV(_name, _id, _parent, _conf, _dtable) \
76 DEF_TYPE(_name, _id, CLK_TYPE_RZT2H_DIV, .conf = _conf, \
77 .parent = _parent, .dtable = _dtable, .flag = 0)
78 #define DEF_MUX(_name, _id, _conf, _parent_names, _num_parents, _mux_flags) \
79 DEF_TYPE(_name, _id, CLK_TYPE_RZT2H_MUX, .conf = _conf, \
80 .parent_names = _parent_names, .num_parents = _num_parents, \
81 .flag = 0, .mux_flags = _mux_flags)
82 #define DEF_DIV_FSELXSPI(_name, _id, _parent, _conf, _dtable) \
83 DEF_TYPE(_name, _id, CLK_TYPE_RZT2H_FSELXSPI, .conf = _conf, \
84 .parent = _parent, .dtable = _dtable, .flag = 0)
85
86 enum clk_ids {
87 /* Core Clock Outputs exported to DT */
> 88 LAST_DT_CORE_CLK = R9A09G077_XSPI_CLK1,
89
90 /* External Input Clocks */
91 CLK_EXTAL,
92
93 /* Internal Core Clocks */
94 CLK_LOCO,
95 CLK_PLL0,
96 CLK_PLL1,
97 CLK_PLL2,
98 CLK_PLL4,
99 CLK_SEL_CLK_PLL0,
100 CLK_SEL_CLK_PLL1,
101 CLK_SEL_CLK_PLL2,
102 CLK_SEL_CLK_PLL4,
103 CLK_PLL4D1,
104 CLK_PLL4D1_DIV3,
105 CLK_PLL4D1_DIV4,
106 CLK_SCI0ASYNC,
107 CLK_SCI1ASYNC,
108 CLK_SCI2ASYNC,
109 CLK_SCI3ASYNC,
110 CLK_SCI4ASYNC,
111 CLK_SCI5ASYNC,
112 CLK_SPI0ASYNC,
113 CLK_SPI1ASYNC,
114 CLK_SPI2ASYNC,
115 CLK_SPI3ASYNC,
116 CLK_DIVSELXSPI0_SCKCR,
117 CLK_DIVSELXSPI1_SCKCR,
118
119 /* Module Clocks */
120 MOD_CLK_BASE,
121 };
122
123 static const struct clk_div_table dtable_1_2[] = {
124 {0, 2},
125 {1, 1},
126 {0, 0},
127 };
128
129 static const struct clk_div_table dtable_6_8_16_32_64[] = {
130 {6, 64},
131 {5, 32},
132 {4, 16},
133 {3, 8},
134 {2, 6},
135 {0, 0},
136 };
137
138 static const struct clk_div_table dtable_24_25_30_32[] = {
139 {0, 32},
140 {1, 30},
141 {2, 25},
142 {3, 24},
143 {0, 0},
144 };
145
146 /* Mux clock tables */
147
148 static const char * const sel_clk_pll0[] = { ".loco", ".pll0" };
149 static const char * const sel_clk_pll1[] = { ".loco", ".pll1" };
150 static const char * const sel_clk_pll2[] = { ".loco", ".pll2" };
151 static const char * const sel_clk_pll4[] = { ".loco", ".pll4" };
152 static const char * const sel_clk_pll4d1_div3_div4[] = { ".pll4d1_div3", ".pll4d1_div4" };
153
154 static const struct cpg_core_clk r9a09g077_core_clks[] __initconst = {
155 /* External Clock Inputs */
156 DEF_INPUT("extal", CLK_EXTAL),
157
158 /* Internal Core Clocks */
159 DEF_RATE(".loco", CLK_LOCO, 1000 * 1000),
160 DEF_FIXED(".pll0", CLK_PLL0, CLK_EXTAL, 1, 48),
161 DEF_FIXED(".pll1", CLK_PLL1, CLK_EXTAL, 1, 40),
162 DEF_FIXED(".pll2", CLK_PLL2, CLK_EXTAL, 1, 32),
163 DEF_FIXED(".pll4", CLK_PLL4, CLK_EXTAL, 1, 96),
164
165 DEF_MUX(".sel_clk_pll0", CLK_SEL_CLK_PLL0, SEL_PLL,
166 sel_clk_pll0, ARRAY_SIZE(sel_clk_pll0), CLK_MUX_READ_ONLY),
167 DEF_MUX(".sel_clk_pll1", CLK_SEL_CLK_PLL1, SEL_PLL,
168 sel_clk_pll1, ARRAY_SIZE(sel_clk_pll1), CLK_MUX_READ_ONLY),
169 DEF_MUX(".sel_clk_pll2", CLK_SEL_CLK_PLL2, SEL_PLL,
170 sel_clk_pll2, ARRAY_SIZE(sel_clk_pll2), CLK_MUX_READ_ONLY),
171 DEF_MUX(".sel_clk_pll4", CLK_SEL_CLK_PLL4, SEL_PLL,
172 sel_clk_pll4, ARRAY_SIZE(sel_clk_pll4), CLK_MUX_READ_ONLY),
173
174 DEF_FIXED(".pll4d1", CLK_PLL4D1, CLK_SEL_CLK_PLL4, 1, 1),
175 DEF_FIXED(".pll4d1_div3", CLK_PLL4D1_DIV3, CLK_PLL4D1, 3, 1),
176 DEF_FIXED(".pll4d1_div4", CLK_PLL4D1_DIV4, CLK_PLL4D1, 4, 1),
177 DEF_DIV(".sci0async", CLK_SCI0ASYNC, CLK_PLL4D1, DIVSCI0ASYNC,
178 dtable_24_25_30_32),
179 DEF_DIV(".sci1async", CLK_SCI1ASYNC, CLK_PLL4D1, DIVSCI1ASYNC,
180 dtable_24_25_30_32),
181 DEF_DIV(".sci2async", CLK_SCI2ASYNC, CLK_PLL4D1, DIVSCI2ASYNC,
182 dtable_24_25_30_32),
183 DEF_DIV(".sci3async", CLK_SCI3ASYNC, CLK_PLL4D1, DIVSCI3ASYNC,
184 dtable_24_25_30_32),
185 DEF_DIV(".sci4async", CLK_SCI4ASYNC, CLK_PLL4D1, DIVSCI4ASYNC,
186 dtable_24_25_30_32),
187 DEF_DIV(".sci5async", CLK_SCI5ASYNC, CLK_PLL4D1, DIVSCI5ASYNC,
188 dtable_24_25_30_32),
189
190 DEF_DIV(".spi0async", CLK_SPI0ASYNC, CLK_PLL4D1, DIVSPI0ASYNC,
191 dtable_24_25_30_32),
192 DEF_DIV(".spi1async", CLK_SPI1ASYNC, CLK_PLL4D1, DIVSPI1ASYNC,
193 dtable_24_25_30_32),
194 DEF_DIV(".spi2async", CLK_SPI2ASYNC, CLK_PLL4D1, DIVSPI2ASYNC,
195 dtable_24_25_30_32),
196 DEF_DIV(".spi3async", CLK_SPI3ASYNC, CLK_PLL4D1, DIVSPI3ASYNC,
197 dtable_24_25_30_32),
198
199 DEF_MUX(".divselxspi0", CLK_DIVSELXSPI0_SCKCR, DIVSEL_XSPI0,
200 sel_clk_pll4d1_div3_div4,
201 ARRAY_SIZE(sel_clk_pll4d1_div3_div4), 0),
202 DEF_MUX(".divselxspi1", CLK_DIVSELXSPI1_SCKCR, DIVSEL_XSPI1,
203 sel_clk_pll4d1_div3_div4,
204 ARRAY_SIZE(sel_clk_pll4d1_div3_div4), 0),
205
206 /* Core output clk */
207 DEF_DIV("CA55C0", R9A09G077_CLK_CA55C0, CLK_SEL_CLK_PLL0, DIVCA55C0,
208 dtable_1_2),
209 DEF_DIV("CA55C1", R9A09G077_CLK_CA55C1, CLK_SEL_CLK_PLL0, DIVCA55C1,
210 dtable_1_2),
211 DEF_DIV("CA55C2", R9A09G077_CLK_CA55C2, CLK_SEL_CLK_PLL0, DIVCA55C2,
212 dtable_1_2),
213 DEF_DIV("CA55C3", R9A09G077_CLK_CA55C3, CLK_SEL_CLK_PLL0, DIVCA55C3,
214 dtable_1_2),
215 DEF_DIV("CA55S", R9A09G077_CLK_CA55S, CLK_SEL_CLK_PLL0, DIVCA55S,
216 dtable_1_2),
217 DEF_FIXED("PCLKGPTL", R9A09G077_CLK_PCLKGPTL, CLK_SEL_CLK_PLL1, 2, 1),
218 DEF_FIXED("PCLKH", R9A09G077_CLK_PCLKH, CLK_SEL_CLK_PLL1, 4, 1),
219 DEF_FIXED("PCLKM", R9A09G077_CLK_PCLKM, CLK_SEL_CLK_PLL1, 8, 1),
220 DEF_FIXED("PCLKL", R9A09G077_CLK_PCLKL, CLK_SEL_CLK_PLL1, 16, 1),
221 DEF_FIXED("PCLKAH", R9A09G077_CLK_PCLKAH, CLK_PLL4D1, 6, 1),
222 DEF_FIXED("PCLKAM", R9A09G077_CLK_PCLKAM, CLK_PLL4D1, 12, 1),
223 DEF_FIXED("SDHI_CLKHS", R9A09G077_SDHI_CLKHS, CLK_SEL_CLK_PLL2, 1, 1),
224 DEF_FIXED("USB_CLK", R9A09G077_USB_CLK, CLK_PLL4D1, 48, 1),
225 DEF_FIXED("ETCLKA", R9A09G077_ETCLKA, CLK_SEL_CLK_PLL1, 5, 1),
226 DEF_FIXED("ETCLKB", R9A09G077_ETCLKB, CLK_SEL_CLK_PLL1, 8, 1),
227 DEF_FIXED("ETCLKC", R9A09G077_ETCLKC, CLK_SEL_CLK_PLL1, 10, 1),
228 DEF_FIXED("ETCLKD", R9A09G077_ETCLKD, CLK_SEL_CLK_PLL1, 20, 1),
229 DEF_FIXED("ETCLKE", R9A09G077_ETCLKE, CLK_SEL_CLK_PLL1, 40, 1),
> 230 DEF_DIV_FSELXSPI("XSPI_CLK0", R9A09G077_XSPI_CLK0, CLK_DIVSELXSPI0_SCKCR,
231 FSELXSPI0, dtable_6_8_16_32_64),
232 DEF_DIV_FSELXSPI("XSPI_CLK1", R9A09G077_XSPI_CLK1, CLK_DIVSELXSPI1_SCKCR,
233 FSELXSPI1, dtable_6_8_16_32_64),
234 };
235
--
0-DAY CI Kernel Test Service
https://github.com/intel/lkp-tests/wiki
next prev parent reply other threads:[~2025-11-18 10:01 UTC|newest]
Thread overview: 5+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-11-17 20:56 [PATCH v3] clk: renesas: r9a09g077: Add xSPI core and module clocks Prabhakar
2025-11-18 10:00 ` kernel test robot [this message]
2025-11-18 10:11 ` kernel test robot
2025-11-24 16:14 ` Geert Uytterhoeven
2025-11-25 22:59 ` Lad, Prabhakar
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=202511181758.cZTukDMh-lkp@intel.com \
--to=lkp@intel.com \
--cc=biju.das.jz@bp.renesas.com \
--cc=fabrizio.castro.jz@renesas.com \
--cc=geert+renesas@glider.be \
--cc=linux-clk@vger.kernel.org \
--cc=linux-kernel@vger.kernel.org \
--cc=linux-renesas-soc@vger.kernel.org \
--cc=mturquette@baylibre.com \
--cc=oe-kbuild-all@lists.linux.dev \
--cc=prabhakar.csengg@gmail.com \
--cc=prabhakar.mahadev-lad.rj@bp.renesas.com \
--cc=sboyd@kernel.org \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is an external index of several public inboxes,
see mirroring instructions on how to clone and mirror
all data and code used by this external index.