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From: Alex Deucher <alexander.deucher@amd.com>
To: <amd-gfx@lists.freedesktop.org>
Cc: Mukul Joshi <mukul.joshi@amd.com>,
	Philip Yang <Philip.Yang@amd.com>,
	"Alex Deucher" <alexander.deucher@amd.com>
Subject: [PATCH 3/7] drm/amdgpu: Add per-ASIC PTE init flag
Date: Wed, 19 Nov 2025 10:05:56 -0500	[thread overview]
Message-ID: <20251119150600.3663611-4-alexander.deucher@amd.com> (raw)
In-Reply-To: <20251119150600.3663611-1-alexander.deucher@amd.com>

From: Mukul Joshi <mukul.joshi@amd.com>

On GFX12.1, default PTE setup needs an additional bit to be
set. Add PTE initialization flags to handle setup default PTE
on a per-ASIC basis.
While at it, fixup the coding style too.

Signed-off-by: Mukul Joshi <mukul.joshi@amd.com>
Reviewed-by: Philip Yang <Philip.Yang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.h   | 1 +
 drivers/gpu/drm/amd/amdgpu/amdgpu_vm_pt.c | 4 ++--
 drivers/gpu/drm/amd/amdgpu/gmc_v12_0.c    | 1 +
 3 files changed, 4 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.h
index 130310ae3c59e..98514fe0a5f68 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.h
@@ -351,6 +351,7 @@ struct amdgpu_gmc {
 	u64 MC_VM_MX_L1_TLB_CNTL;
 
 	u64 noretry_flags;
+	u64 init_pte_flags;
 
 	bool flush_tlb_needs_extra_type_0;
 	bool flush_tlb_needs_extra_type_2;
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm_pt.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm_pt.c
index f6ffc207ec2a6..8bd411ba8b218 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm_pt.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm_pt.c
@@ -366,6 +366,7 @@ int amdgpu_vm_pt_clear(struct amdgpu_device *adev, struct amdgpu_vm *vm,
 	struct amdgpu_bo *ancestor = &vmbo->bo;
 	unsigned int entries;
 	struct amdgpu_bo *bo = &vmbo->bo;
+	uint64_t value = 0, flags = 0;
 	uint64_t addr;
 	int r, idx;
 
@@ -402,7 +403,6 @@ int amdgpu_vm_pt_clear(struct amdgpu_device *adev, struct amdgpu_vm *vm,
 
 	addr = 0;
 
-	uint64_t value = 0, flags = 0;
 	if (adev->asic_type >= CHIP_VEGA10) {
 		if (level != AMDGPU_VM_PTB) {
 			/* Handle leaf PDEs as PTEs */
@@ -411,7 +411,7 @@ int amdgpu_vm_pt_clear(struct amdgpu_device *adev, struct amdgpu_vm *vm,
 					      &value, &flags);
 		} else {
 			/* Workaround for fault priority problem on GMC9 */
-			flags = AMDGPU_PTE_EXECUTABLE;
+			flags = AMDGPU_PTE_EXECUTABLE | adev->gmc.init_pte_flags;
 		}
 	}
 
diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v12_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v12_0.c
index 3cb61d2c58f95..ab7d3469c5c50 100644
--- a/drivers/gpu/drm/amd/amdgpu/gmc_v12_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gmc_v12_0.c
@@ -627,6 +627,7 @@ static int gmc_v12_0_early_init(struct amdgpu_ip_block *ip_block)
 	switch (amdgpu_ip_version(adev, GC_HWIP, 0)) {
 	case IP_VERSION(12, 1, 0):
 		gmc_v12_1_set_gmc_funcs(adev);
+		adev->gmc.init_pte_flags = AMDGPU_PTE_IS_PTE;
 		break;
 	default:
 		gmc_v12_0_set_gmc_funcs(adev);
-- 
2.51.1


  parent reply	other threads:[~2025-11-19 15:06 UTC|newest]

Thread overview: 8+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2025-11-19 15:05 [PATCH 0/7] Add gmc 12.1 support Alex Deucher
2025-11-19 15:05 ` [PATCH 1/7] drm/amdgpu: Add gmc v12_1 support Alex Deucher
2025-11-19 15:05 ` [PATCH 2/7] drm/amdgpu: Add gmc v12_1 gmc callbacks Alex Deucher
2025-11-19 15:05 ` Alex Deucher [this message]
2025-11-19 15:05 ` [PATCH 4/7] drm/amdgpu: Always set snoop bit in PDE on GFX 12.1 Alex Deucher
2025-11-19 15:05 ` [PATCH 5/7] drm/amdgpu: Enable PDE.C usage " Alex Deucher
2025-11-19 15:05 ` [PATCH 6/7] drm/amdkfd: Fix PTE clearing during SVM unmap " Alex Deucher
2025-11-19 15:06 ` [PATCH 7/7] drm/amdgpu: Add gmc v12_1_0 to discovery list Alex Deucher

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