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From: Martin Schiller <ms@dev.tdt.de>
To: tony.luck@intel.com, peterz@infradead.org, mingo@redhat.com,
	acme@kernel.org, namhyung@kernel.org, mark.rutland@arm.com,
	alexander.shishkin@linux.intel.com, jolsa@kernel.org,
	irogers@google.com, adrian.hunter@intel.com,
	james.clark@linaro.org, tglx@linutronix.de, bp@alien8.de,
	dave.hansen@linux.intel.com
Cc: x86@kernel.org, hpa@zytor.com, linux-perf-users@vger.kernel.org,
	linux-kernel@vger.kernel.org, fe@dev.tdt.de,
	Martin Schiller <ms@dev.tdt.de>
Subject: [PATCH 1/3] perf/x86/msr: Add Airmont NP
Date: Mon, 24 Nov 2025 08:48:44 +0100	[thread overview]
Message-ID: <20251124074846.9653-2-ms@dev.tdt.de> (raw)
In-Reply-To: <20251124074846.9653-1-ms@dev.tdt.de>

Like Airmont, the Airmont NP (aka Intel / MaxLinear Lightning Mountain)
supports SMI_COUNT MSR.

Signed-off-by: Martin Schiller <ms@dev.tdt.de>
---
 arch/x86/events/msr.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/arch/x86/events/msr.c b/arch/x86/events/msr.c
index 7f5007a4752a..8052596b8503 100644
--- a/arch/x86/events/msr.c
+++ b/arch/x86/events/msr.c
@@ -78,6 +78,7 @@ static bool test_intel(int idx, void *data)
 	case INTEL_ATOM_SILVERMONT:
 	case INTEL_ATOM_SILVERMONT_D:
 	case INTEL_ATOM_AIRMONT:
+	case INTEL_ATOM_AIRMONT_NP:
 
 	case INTEL_ATOM_GOLDMONT:
 	case INTEL_ATOM_GOLDMONT_D:
-- 
2.47.3


  reply	other threads:[~2025-11-24  8:06 UTC|newest]

Thread overview: 9+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2025-11-24  7:48 [PATCH 0/3] perf/x86: Add Airmont NP Martin Schiller
2025-11-24  7:48 ` Martin Schiller [this message]
2025-12-17 12:38   ` [tip: perf/core] perf/x86/msr: " tip-bot2 for Martin Schiller
2025-11-24  7:48 ` [PATCH 2/3] perf/x86/intel: " Martin Schiller
2025-12-17 12:38   ` [tip: perf/core] " tip-bot2 for Martin Schiller
2025-11-24  7:48 ` [PATCH 3/3] perf/x86/cstate: " Martin Schiller
2025-12-17 12:37   ` [tip: perf/core] " tip-bot2 for Martin Schiller
2025-11-25  7:44 ` [PATCH 0/3] perf/x86: " Mi, Dapeng
2025-12-17  7:33   ` Martin Schiller

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