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Tue, 25 Nov 2025 07:39:12 -0800 (PST) Received: from localhost ([140.82.166.162]) by smtp.gmail.com with ESMTPSA id ca18e2360f4ac-949385ae254sm617805339f.1.2025.11.25.07.39.11 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 25 Nov 2025 07:39:11 -0800 (PST) Date: Tue, 25 Nov 2025 09:39:10 -0600 From: Andrew Jones To: Daniel Henrique Barboza Cc: Chao Liu , alistair.francis@wdc.com, liwei1518@gmail.com, palmer@dabbelt.com, qemu-devel@nongnu.org, qemu-riscv@nongnu.org, wu.fei9@sanechips.com.cn, zhiwei_liu@linux.alibaba.com, xiaofan@iscas.ac.cn, wangjingwei@iscas.ac.cn Subject: Re: [PATCH v4 3/5] hw/riscv: experimental server platform reference machine Message-ID: <20251125-3e644247d1d73ebad131f69a@orel> References: <20251111182944.2895892-4-dbarboza@ventanamicro.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: Received-SPF: pass client-ip=2607:f8b0:4864:20::d44; envelope-from=ajones@ventanamicro.com; helo=mail-io1-xd44.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org On Tue, Nov 25, 2025 at 08:24:22AM -0300, Daniel Henrique Barboza wrote: ... > So, in the latest spec, section 2.1 RISC-V Harts: > > https://github.com/riscv-non-isa/riscv-server-platform/releases/download/v0.9-rc3/riscv-server-platform.pdf > > There's a set of "rules" that each hart should or can follow. Rule RVA_010 states: > > "The RISC-V application processor harts in the SoC MUST support the RVA23S64 ISA > profile [6]." > > The next rule, RVA_020: > > "The RISC-V application processor harts in the SoC MUST support the following > extensions: > - Sv48 > - Sdtrig [7] > - Sdext [7] > - Zkr > - Ssccfg > - Ssstrict [6] > - Ssaia [8]" > > > I take it that the wording used, **MUST**, indicates that RVA_020 is mandatory so we should > in fact support sv48. In this case we can change the default to sv48 without problems > > > Drew, is this a fair interpretation? Thanks, Yes. The server platform spec is based on rva23, but also mandates additional extensions beyond what's mandated by the profile, including sv48. (And this is why I stated the default should be sv48 when pointing out that it shouldn't be sv57[1]). [1] https://lore.kernel.org/all/20251111-e4f4062f326aef78ef820d00@orel/ Thanks, drew