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CTRY:US; LANG:en; SCL:1; SRV:; IPV:NLI; SFV:NSPM; H:mail.nvidia.com; PTR:dc6edge2.nvidia.com; CAT:NONE; SFS:(13230040)(36860700013)(1800799024)(376014)(82310400026); DIR:OUT; SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 01 Dec 2025 23:41:31.1320 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 716f7283-ddd9-4959-19a5-08de313327bb X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[216.228.117.161]; Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: DS1PEPF0001708F.namprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DS0PR12MB8813 X-BeenThere: nouveau@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Nouveau development list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: nouveau-bounces@lists.freedesktop.org Sender: "Nouveau" Implement the trait object FalconUCodeDescriptor to handle the two versions of the Falcon microcode descriptor. Introduce the FalconUCodeDescriptor trait to provide a unified interface for accessing fields in both V2 and V3 Falcon microcode descriptor formats. This replaces repetitive match statements in each accessor method with a single as_descriptor() method that returns a trait object, reducing boilerplate and making it easier to add new accessors in the future. However, not all match states can be eliminated. The FalconLoadParams implementation still needs to match on the version because different fields of the descriptor are used depending on the version. Signed-off-by: Timur Tabi --- drivers/gpu/nova-core/firmware.rs | 91 ++++++++++++++++++------------- 1 file changed, 54 insertions(+), 37 deletions(-) diff --git a/drivers/gpu/nova-core/firmware.rs b/drivers/gpu/nova-core/firmware.rs index 3008d18f9313..2ad56a387a79 100644 --- a/drivers/gpu/nova-core/firmware.rs +++ b/drivers/gpu/nova-core/firmware.rs @@ -125,13 +125,55 @@ pub(crate) enum FalconUCodeDesc { V3(FalconUCodeDescV3), } +// First define trait +pub(crate) trait FalconUCodeDescriptor { + fn hdr(&self) -> u32; + fn imem_load_size(&self) -> u32; + fn interface_offset(&self) -> u32; + fn dmem_load_size(&self) -> u32; + fn pkc_data_offset(&self) -> u32; + fn engine_id_mask(&self) -> u16; + fn ucode_id(&self) -> u8; + fn signature_count(&self) -> u8; + fn signature_versions(&self) -> u16; +} + +impl FalconUCodeDescriptor for FalconUCodeDescV2 { + fn hdr(&self) -> u32 { self.hdr } + fn imem_load_size(&self) -> u32 { self.imem_load_size } + fn interface_offset(&self) -> u32 { self.interface_offset } + fn dmem_load_size(&self) -> u32 { self.dmem_load_size } + fn pkc_data_offset(&self) -> u32 { 0 } + fn engine_id_mask(&self) -> u16 { 0 } + fn ucode_id(&self) -> u8 { 0 } + fn signature_count(&self) -> u8 { 0 } + fn signature_versions(&self) -> u16 { 0 } +} + +impl FalconUCodeDescriptor for FalconUCodeDescV3 { + fn hdr(&self) -> u32 { self.hdr } + fn imem_load_size(&self) -> u32 { self.imem_load_size } + fn interface_offset(&self) -> u32 { self.interface_offset } + fn dmem_load_size(&self) -> u32 { self.dmem_load_size } + fn pkc_data_offset(&self) -> u32 { self.pkc_data_offset } + fn engine_id_mask(&self) -> u16 { self.engine_id_mask } + fn ucode_id(&self) -> u8 { self.ucode_id } + fn signature_count(&self) -> u8 { self.signature_count } + fn signature_versions(&self) -> u16 { self.signature_versions } +} + impl FalconUCodeDesc { + // Return trait object, the only match needed. + pub(crate) fn as_descriptor(&self) -> &dyn FalconUCodeDescriptor { + match self { + FalconUCodeDesc::V2(v2) => v2, + FalconUCodeDesc::V3(v3) => v3, + } + } + /// Returns the size in bytes of the header. pub(crate) fn size(&self) -> usize { - let hdr = match self { - FalconUCodeDesc::V2(v2) => v2.hdr, - FalconUCodeDesc::V3(v3) => v3.hdr, - }; + let hdr = self.as_descriptor().hdr(); const HDR_SIZE_SHIFT: u32 = 16; const HDR_SIZE_MASK: u32 = 0xffff0000; @@ -139,60 +181,35 @@ pub(crate) fn size(&self) -> usize { } pub(crate) fn imem_load_size(&self) -> u32 { - match self { - FalconUCodeDesc::V2(v2) => v2.imem_load_size, - FalconUCodeDesc::V3(v3) => v3.imem_load_size, - } + self.as_descriptor().imem_load_size() } pub(crate) fn interface_offset(&self) -> u32 { - match self { - FalconUCodeDesc::V2(v2) => v2.interface_offset, - FalconUCodeDesc::V3(v3) => v3.interface_offset, - } + self.as_descriptor().interface_offset() } - pub(crate) fn dmem_load_size(&self) -> u32 { - match self { - FalconUCodeDesc::V2(v2) => v2.dmem_load_size, - FalconUCodeDesc::V3(v3) => v3.dmem_load_size, - } + self.as_descriptor().dmem_load_size() } pub(crate) fn pkc_data_offset(&self) -> u32 { - match self { - FalconUCodeDesc::V2(_v2) => 0, - FalconUCodeDesc::V3(v3) => v3.pkc_data_offset, - } + self.as_descriptor().pkc_data_offset() } pub(crate) fn engine_id_mask(&self) -> u16 { - match self { - FalconUCodeDesc::V2(_v2) => 0, - FalconUCodeDesc::V3(v3) => v3.engine_id_mask, - } + self.as_descriptor().engine_id_mask() } pub(crate) fn ucode_id(&self) -> u8 { - match self { - FalconUCodeDesc::V2(_v2) => 0, - FalconUCodeDesc::V3(v3) => v3.ucode_id, - } + self.as_descriptor().ucode_id() } pub(crate) fn signature_count(&self) -> u8 { - match self { - FalconUCodeDesc::V2(_v2) => 0, - FalconUCodeDesc::V3(v3) => v3.signature_count, - } + self.as_descriptor().signature_count() } pub(crate) fn signature_versions(&self) -> u16 { - match self { - FalconUCodeDesc::V2(_v2) => 0, - FalconUCodeDesc::V3(v3) => v3.signature_versions, - } + self.as_descriptor().signature_versions() } } -- 2.52.0