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Message-ID: <202512101331.7lvdnT3K-lkp@intel.com> Precedence: bulk X-Mailing-List: oe-kbuild@lists.linux.dev List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline BCC: lkp@intel.com CC: oe-kbuild-all@lists.linux.dev CC: linux-kernel@vger.kernel.org TO: Akhil P Oommen CC: Rob Clark tree: https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git master head: c9b47175e9131118e6f221cc8fb81397d62e7c91 commit: 288a932008925644d8d0ca69bf7a69a0dce82dc5 drm/msm/adreno: Introduce A8x GPU Support date: 3 weeks ago :::::: branch date: 7 hours ago :::::: commit date: 3 weeks ago config: arm64-randconfig-r072-20251207 (https://download.01.org/0day-ci/archive/20251210/202512101331.7lvdnT3K-lkp@intel.com/config) compiler: clang version 22.0.0git (https://github.com/llvm/llvm-project a805147ac1ba123916de182babb0831fbb148756) If you fix the issue in a separate patch/commit (i.e. not just a new version of the same patch/commit), kindly add following tags | Reported-by: kernel test robot | Reported-by: Dan Carpenter | Closes: https://lore.kernel.org/r/202512101331.7lvdnT3K-lkp@intel.com/ smatch warnings: drivers/gpu/drm/msm/adreno/a8xx_gpu.c:255 a8xx_set_cp_protect() error: uninitialized symbol 'final_cfg'. vim +/final_cfg +255 drivers/gpu/drm/msm/adreno/a8xx_gpu.c 288a9320089256 Akhil P Oommen 2025-11-18 221 288a9320089256 Akhil P Oommen 2025-11-18 222 static void a8xx_set_cp_protect(struct msm_gpu *gpu) 288a9320089256 Akhil P Oommen 2025-11-18 223 { 288a9320089256 Akhil P Oommen 2025-11-18 224 struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu); 288a9320089256 Akhil P Oommen 2025-11-18 225 const struct adreno_protect *protect = adreno_gpu->info->a6xx->protect; 288a9320089256 Akhil P Oommen 2025-11-18 226 u32 cntl, final_cfg; 288a9320089256 Akhil P Oommen 2025-11-18 227 unsigned int i; 288a9320089256 Akhil P Oommen 2025-11-18 228 288a9320089256 Akhil P Oommen 2025-11-18 229 cntl = A8XX_CP_PROTECT_CNTL_PIPE_ACCESS_PROT_EN | 288a9320089256 Akhil P Oommen 2025-11-18 230 A8XX_CP_PROTECT_CNTL_PIPE_ACCESS_FAULT_ON_VIOL_EN | 288a9320089256 Akhil P Oommen 2025-11-18 231 A8XX_CP_PROTECT_CNTL_PIPE_LAST_SPAN_INF_RANGE | 288a9320089256 Akhil P Oommen 2025-11-18 232 A8XX_CP_PROTECT_CNTL_PIPE_HALT_SQE_RANGE__MASK; 288a9320089256 Akhil P Oommen 2025-11-18 233 /* 288a9320089256 Akhil P Oommen 2025-11-18 234 * Enable access protection to privileged registers, fault on an access 288a9320089256 Akhil P Oommen 2025-11-18 235 * protect violation and select the last span to protect from the start 288a9320089256 Akhil P Oommen 2025-11-18 236 * address all the way to the end of the register address space 288a9320089256 Akhil P Oommen 2025-11-18 237 */ 288a9320089256 Akhil P Oommen 2025-11-18 238 a8xx_write_pipe(gpu, PIPE_BR, REG_A8XX_CP_PROTECT_CNTL_PIPE, cntl); 288a9320089256 Akhil P Oommen 2025-11-18 239 a8xx_write_pipe(gpu, PIPE_BV, REG_A8XX_CP_PROTECT_CNTL_PIPE, cntl); 288a9320089256 Akhil P Oommen 2025-11-18 240 288a9320089256 Akhil P Oommen 2025-11-18 241 a8xx_aperture_clear(gpu); 288a9320089256 Akhil P Oommen 2025-11-18 242 288a9320089256 Akhil P Oommen 2025-11-18 243 for (i = 0; i < protect->count; i++) { 288a9320089256 Akhil P Oommen 2025-11-18 244 /* Intentionally skip writing to some registers */ 288a9320089256 Akhil P Oommen 2025-11-18 245 if (protect->regs[i]) { 288a9320089256 Akhil P Oommen 2025-11-18 246 gpu_write(gpu, REG_A8XX_CP_PROTECT_GLOBAL(i), protect->regs[i]); 288a9320089256 Akhil P Oommen 2025-11-18 247 final_cfg = protect->regs[i]; 288a9320089256 Akhil P Oommen 2025-11-18 248 } 288a9320089256 Akhil P Oommen 2025-11-18 249 } 288a9320089256 Akhil P Oommen 2025-11-18 250 288a9320089256 Akhil P Oommen 2025-11-18 251 /* 288a9320089256 Akhil P Oommen 2025-11-18 252 * Last span feature is only supported on PIPE specific register. 288a9320089256 Akhil P Oommen 2025-11-18 253 * So update those here 288a9320089256 Akhil P Oommen 2025-11-18 254 */ 288a9320089256 Akhil P Oommen 2025-11-18 @255 a8xx_write_pipe(gpu, PIPE_BR, REG_A8XX_CP_PROTECT_PIPE(protect->count_max), final_cfg); 288a9320089256 Akhil P Oommen 2025-11-18 256 a8xx_write_pipe(gpu, PIPE_BV, REG_A8XX_CP_PROTECT_PIPE(protect->count_max), final_cfg); 288a9320089256 Akhil P Oommen 2025-11-18 257 288a9320089256 Akhil P Oommen 2025-11-18 258 a8xx_aperture_clear(gpu); 288a9320089256 Akhil P Oommen 2025-11-18 259 } 288a9320089256 Akhil P Oommen 2025-11-18 260 -- 0-DAY CI Kernel Test Service https://github.com/intel/lkp-tests/wiki