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Miller" , Eric Dumazet , Jakub Kicinski , "Paolo Abeni" , Satananda Burla , "Abhijit Ayarekar" Subject: [PATCH net v1 1/3] octeon_ep: disable per ring interrupts Date: Fri, 12 Dec 2025 12:23:00 +0000 Message-ID: <20251212122304.2562229-2-vimleshk@marvell.com> X-Mailer: git-send-email 2.47.3 In-Reply-To: <20251212122304.2562229-1-vimleshk@marvell.com> References: <20251212122304.2562229-1-vimleshk@marvell.com> Precedence: bulk X-Mailing-List: netdev@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-Proofpoint-GUID: 0ElD2GWRArAuWo_HAfHtdddTO5sFXqoD X-Authority-Analysis: v=2.4 cv=QtZTHFyd c=1 sm=1 tr=0 ts=693c093c cx=c_pps a=gIfcoYsirJbf48DBMSPrZA==:117 a=gIfcoYsirJbf48DBMSPrZA==:17 a=wP3pNCr1ah4A:10 a=VkNPw1HP01LnGYTKEx00:22 a=M5GUcnROAAAA:8 a=e4-9pDM4cGMqtLHJL1gA:9 a=OBjm3rFKGHvpk9ecZwUJ:22 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUxMjEyMDA5NiBTYWx0ZWRfX/5zx3RG2ZAW4 IXzlpxFBLqjySVPzUxCk9jZvtJb6u8lSGJCmOPjU/k5sctCM8NLryxqjtg88T90hmXvS+rLQvOV iMIZXpxZjimmpQhO2onJ4DXc0uck9ym3LLmkMpiwBTvdgkf04RzpcvG889iBYIjWAGkk9ThxMUQ mCtgagz1Pb4vuerYgN0f45iveC6J5nU/Kzp9RUczWbhJYupw7qqMdRip4Tu0XbTFFYkbB3DdxqB BpY/UUr+NIvSL/52dE7bwM0SJ1SJhVTgCxfIGdJWNSq2PBvzSuzzc7yjKSjMYtqoZLsNVhRFkIu z9CVu5jtwQK51L7iBjGOlBWUHI6JbFR+l6jlH9eECRq7l4unBwYevLnhQSHtsFQlPBmc6McaYQs dA8Pq6PaTdtu/85qP157lAcH3IOWxg== X-Proofpoint-ORIG-GUID: 0ElD2GWRArAuWo_HAfHtdddTO5sFXqoD X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1121,Hydra:6.1.9,FMLib:17.12.100.49 definitions=2025-12-12_03,2025-12-11_01,2025-10-01_01 Disable the MSI-X per ring interrupt for every PF ring when PF netdev goes down. Fixes: 1f2c2d0cee023 ("octeon_ep: add hardware configuration APIs") Signed-off-by: Sathesh Edara Signed-off-by: Shinas Rasheed Signed-off-by: Vimlesh Kumar --- .../net/ethernet/marvell/octeon_ep/octep_cn9k_pf.c | 12 ++++++++++-- .../net/ethernet/marvell/octeon_ep/octep_cnxk_pf.c | 12 ++++++++++-- 2 files changed, 20 insertions(+), 4 deletions(-) diff --git a/drivers/net/ethernet/marvell/octeon_ep/octep_cn9k_pf.c b/drivers/net/ethernet/marvell/octeon_ep/octep_cn9k_pf.c index b5805969404f..db8ae1734e1b 100644 --- a/drivers/net/ethernet/marvell/octeon_ep/octep_cn9k_pf.c +++ b/drivers/net/ethernet/marvell/octeon_ep/octep_cn9k_pf.c @@ -696,14 +696,22 @@ static void octep_enable_interrupts_cn93_pf(struct octep_device *oct) /* Disable all interrupts */ static void octep_disable_interrupts_cn93_pf(struct octep_device *oct) { - u64 intr_mask = 0ULL; + u64 reg_val, intr_mask = 0ULL; int srn, num_rings, i; srn = CFG_GET_PORTS_PF_SRN(oct->conf); num_rings = CFG_GET_PORTS_ACTIVE_IO_RINGS(oct->conf); - for (i = 0; i < num_rings; i++) + for (i = 0; i < num_rings; i++) { intr_mask |= (0x1ULL << (srn + i)); + reg_val = octep_read_csr64(oct, CN93_SDP_R_IN_INT_LEVELS(srn + i)); + reg_val &= ~(0x1ULL << 62); + octep_write_csr64(oct, CN93_SDP_R_IN_INT_LEVELS(srn + i), reg_val); + + reg_val = octep_read_csr64(oct, CN93_SDP_R_OUT_INT_LEVELS(srn + i)); + reg_val &= ~(0x1ULL << 62); + octep_write_csr64(oct, CN93_SDP_R_OUT_INT_LEVELS(srn + i), reg_val); + } octep_write_csr64(oct, CN93_SDP_EPF_IRERR_RINT_ENA_W1C, intr_mask); octep_write_csr64(oct, CN93_SDP_EPF_ORERR_RINT_ENA_W1C, intr_mask); diff --git a/drivers/net/ethernet/marvell/octeon_ep/octep_cnxk_pf.c b/drivers/net/ethernet/marvell/octeon_ep/octep_cnxk_pf.c index 5de0b5ecbc5f..6369c4dedf46 100644 --- a/drivers/net/ethernet/marvell/octeon_ep/octep_cnxk_pf.c +++ b/drivers/net/ethernet/marvell/octeon_ep/octep_cnxk_pf.c @@ -720,14 +720,22 @@ static void octep_enable_interrupts_cnxk_pf(struct octep_device *oct) /* Disable all interrupts */ static void octep_disable_interrupts_cnxk_pf(struct octep_device *oct) { - u64 intr_mask = 0ULL; + u64 reg_val, intr_mask = 0ULL; int srn, num_rings, i; srn = CFG_GET_PORTS_PF_SRN(oct->conf); num_rings = CFG_GET_PORTS_ACTIVE_IO_RINGS(oct->conf); - for (i = 0; i < num_rings; i++) + for (i = 0; i < num_rings; i++) { intr_mask |= (0x1ULL << (srn + i)); + reg_val = octep_read_csr64(oct, CNXK_SDP_R_IN_INT_LEVELS(srn + i)); + reg_val &= ~(0x1ULL << 62); + octep_write_csr64(oct, CNXK_SDP_R_IN_INT_LEVELS(srn + i), reg_val); + + reg_val = octep_read_csr64(oct, CNXK_SDP_R_OUT_INT_LEVELS(srn + i)); + reg_val &= ~(0x1ULL << 62); + octep_write_csr64(oct, CNXK_SDP_R_OUT_INT_LEVELS(srn + i), reg_val); + } octep_write_csr64(oct, CNXK_SDP_EPF_IRERR_RINT_ENA_W1C, intr_mask); octep_write_csr64(oct, CNXK_SDP_EPF_ORERR_RINT_ENA_W1C, intr_mask); -- 2.47.0