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From: Imre Deak <imre.deak@intel.com>
To: <intel-gfx@lists.freedesktop.org>, <intel-xe@lists.freedesktop.org>
Cc: Luca Coelho <luciano.coelho@intel.com>
Subject: [PATCH 07/16] drm/i915/dp: Fix BW check in is_bw_sufficient_for_dsc_config()
Date: Mon, 15 Dec 2025 21:23:47 +0200	[thread overview]
Message-ID: <20251215192357.172201-8-imre.deak@intel.com> (raw)
In-Reply-To: <20251215192357.172201-1-imre.deak@intel.com>

is_bw_sufficient_for_dsc_config() should return true if the required BW
equals the available BW, make it so.

Reviewed-by: Luca Coelho <luciano.coelho@intel.com>
Signed-off-by: Imre Deak <imre.deak@intel.com>
---
 drivers/gpu/drm/i915/display/intel_dp.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
index a9f0485dbe646..ec4f64090a77b 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -2029,7 +2029,7 @@ static bool is_bw_sufficient_for_dsc_config(int dsc_bpp_x16, u32 link_clock,
 	available_bw = (link_clock * lane_count * timeslots * 16)  / 8;
 	required_bw = dsc_bpp_x16 * (intel_dp_mode_to_fec_clock(mode_clock));
 
-	return available_bw > required_bw;
+	return available_bw >= required_bw;
 }
 
 static int dsc_compute_link_config(struct intel_dp *intel_dp,
-- 
2.49.1


  parent reply	other threads:[~2025-12-15 19:24 UTC|newest]

Thread overview: 28+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2025-12-15 19:23 [PATCH 00/16] drm/i915/dp: Clean up link BW/DSC slice config computation (fixes) Imre Deak
2025-12-15 19:23 ` [PATCH 01/16] drm/dp: Parse all DSC slice count caps for eDP 1.5 Imre Deak
2025-12-15 19:23 ` [PATCH 02/16] drm/dp: Add drm_dp_dsc_sink_slice_count_mask() Imre Deak
2025-12-15 19:23 ` [PATCH 03/16] drm/i915/dp: Fix DSC sink's slice count capability check Imre Deak
2025-12-15 19:23 ` [PATCH 04/16] drm/i915/dp: Return a fixed point BPP value from intel_dp_output_bpp() Imre Deak
2025-12-15 19:23 ` [PATCH 05/16] drm/i915/dp: Use a mode's crtc_clock vs. clock during state computation Imre Deak
2025-12-15 19:23 ` [PATCH 06/16] drm/i915/dp: Factor out intel_dp_link_bw_overhead() Imre Deak
2025-12-15 19:23 ` Imre Deak [this message]
2025-12-15 19:23 ` [PATCH 08/16] drm/i915/dp: Use the effective data rate for DP BW calculation Imre Deak
2025-12-15 19:23 ` [PATCH 09/16] drm/i915/dp: Use the effective data rate for DP compressed " Imre Deak
2025-12-15 19:23 ` [PATCH 10/16] drm/i915/dp: Account with MST, SSC BW overhead for uncompressed DP-MST stream BW Imre Deak
2025-12-15 19:23 ` [PATCH 11/16] drm/i915/dp: Account with DSC BW overhead for compressed DP-SST " Imre Deak
2025-12-15 19:23 ` [PATCH 12/16] drm/i915/dp: Account with pipe joiner max compressed BPP limit for DP-MST and eDP Imre Deak
2025-12-15 19:23 ` [PATCH 13/16] drm/i915/dp: Fail state computation for invalid min/max link BPP values Imre Deak
2025-12-15 19:23 ` [PATCH 14/16] drm/i915/dp: Fail state computation for invalid max throughput BPP value Imre Deak
2025-12-15 19:23 ` [PATCH 15/16] drm/i915/dp: Fail state computation for invalid max sink compressed " Imre Deak
2025-12-15 19:23 ` [PATCH 16/16] drm/i915/dp: Fail state computation for invalid DSC source input BPP values Imre Deak
2025-12-15 20:21 ` ✓ i915.CI.BAT: success for drm/i915/dp: Clean up link BW/DSC slice config computation (fixes) Patchwork
2025-12-15 22:16 ` ✗ CI.checkpatch: warning " Patchwork
2025-12-15 22:17 ` ✓ CI.KUnit: success " Patchwork
2025-12-15 22:36 ` ✗ CI.checksparse: warning " Patchwork
2025-12-15 23:31 ` ✓ Xe.CI.BAT: success " Patchwork
2025-12-16  2:20 ` ✓ i915.CI.Full: " Patchwork
2025-12-19 15:21   ` Imre Deak
2025-12-16  9:27 ` ✗ Xe.CI.Full: failure " Patchwork
2025-12-16 17:30 ` [PATCH 00/16] " Imre Deak
2025-12-18 12:00   ` Imre Deak
2025-12-19 13:28     ` Maarten Lankhorst

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