From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id C5356343D6C; Tue, 16 Dec 2025 11:26:35 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1765884395; cv=none; b=QJs1E0AlAjvlLE8RPhr/VYZtCBrxEBg8tDDKw/hMiON7VAD+eK0FWj2H3zsQrEDU8yuZ7VXDQFqHnhKD3FczhMkBiO41zRXN0qbLGUQVh04PVg+wd2V6zNOsbzhMGoFMBhtw7BNn6uhHdX4zwDcbvxB/b3tdmSFee5y65ZkFB4E= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1765884395; c=relaxed/simple; bh=E/VBXHJDWVRyxzUJCZxqYjNh9D+KHxewoJQsMc4/S3Q=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=nZzylCpVy1TU9OSQ0cY3GkCF0HK2zvbColUQ7xAtWZ1+VofK3NP21y1qyg2LMQutr+5j+b+qSddOOoJvEpC8G+f9KJxqV7z2zO1acUoToXBZTOp/RUfFpP5jMo3gxlJ1k4EWYpWZIiWRs15vsiaw/NLkRwzkdXbkWuNrzYIwvyg= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=linuxfoundation.org header.i=@linuxfoundation.org header.b=vyZaIf8/; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=linuxfoundation.org header.i=@linuxfoundation.org header.b="vyZaIf8/" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 26E86C16AAE; Tue, 16 Dec 2025 11:26:34 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=linuxfoundation.org; s=korg; t=1765884395; bh=E/VBXHJDWVRyxzUJCZxqYjNh9D+KHxewoJQsMc4/S3Q=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=vyZaIf8/IIBlhO9rDsrHhrMOn6qIPBxGhRz+48ogfzaYSSa00M8aZE5yOGZ6cLbMH 5gZItwi9xM0ByGgu/W84R9i0vrsdpQ9PnPCFI9Sf9ZNfJBiHm42w6tuz3qngU8Wfu9 vgaqMrieU13PbnGcqkPHMGegmmEOZkA3V66Gdnnc= From: Greg Kroah-Hartman To: stable@vger.kernel.org Cc: Greg Kroah-Hartman , patches@lists.linux.dev, Konrad Dybcio , Akhil P Oommen , Rob Clark , Sasha Levin Subject: [PATCH 6.12 181/354] drm/msm/a6xx: Fix the gemnoc workaround Date: Tue, 16 Dec 2025 12:12:28 +0100 Message-ID: <20251216111327.469863965@linuxfoundation.org> X-Mailer: git-send-email 2.52.0 In-Reply-To: <20251216111320.896758933@linuxfoundation.org> References: <20251216111320.896758933@linuxfoundation.org> User-Agent: quilt/0.69 X-stable: review X-Patchwork-Hint: ignore Precedence: bulk X-Mailing-List: patches@lists.linux.dev List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit 6.12-stable review patch. If anyone has any objections, please let me know. ------------------ From: Akhil P Oommen [ Upstream commit ff7a6de043fce21ea5891311746b16121b385c59 ] Correct the register offset and enable this workaround for all A7x and newer GPUs to match the recommendation. Also, downstream does this w/a after moving the fence to allow mode. So do the same. Fixes: dbfbb376b50c ("drm/msm/a6xx: Add A621 support") Reviewed-by: Konrad Dybcio Signed-off-by: Akhil P Oommen Patchwork: https://patchwork.freedesktop.org/patch/688997/ Message-ID: <20251118-kaana-gpu-support-v4-3-86eeb8e93fb6@oss.qualcomm.com> Signed-off-by: Rob Clark Signed-off-by: Sasha Levin --- drivers/gpu/drm/msm/adreno/a6xx_gmu.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gmu.c b/drivers/gpu/drm/msm/adreno/a6xx_gmu.c index bfb1225a47c50..e2ea50862a413 100644 --- a/drivers/gpu/drm/msm/adreno/a6xx_gmu.c +++ b/drivers/gpu/drm/msm/adreno/a6xx_gmu.c @@ -435,8 +435,9 @@ static void a6xx_gemnoc_workaround(struct a6xx_gmu *gmu) * in the power down sequence not being fully executed. That in turn can * prevent CX_GDSC from collapsing. Assert Qactive to avoid this. */ - if (adreno_is_a621(adreno_gpu) || adreno_is_7c3(adreno_gpu)) - gmu_write(gmu, REG_A6XX_GMU_AO_AHB_FENCE_CTRL, BIT(0)); + if (adreno_is_a7xx(adreno_gpu) || (adreno_is_a621(adreno_gpu) || + adreno_is_7c3(adreno_gpu))) + gmu_write(gmu, REG_A6XX_GPU_GMU_CX_GMU_CX_FALNEXT_INTF, BIT(0)); } /* Let the GMU know that we are about to go into slumber */ @@ -472,10 +473,9 @@ static int a6xx_gmu_notify_slumber(struct a6xx_gmu *gmu) } out: - a6xx_gemnoc_workaround(gmu); - /* Put fence into allow mode */ gmu_write(gmu, REG_A6XX_GMU_AO_AHB_FENCE_CTRL, 0); + a6xx_gemnoc_workaround(gmu); return ret; } -- 2.51.0