From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 8DF81362129; Tue, 16 Dec 2025 12:22:18 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1765887738; cv=none; b=Q5JhH5QicgIbUdr4jY7dyYWac9Ix4dDSQRmqyel9PW8lJ26dQ6VpA1FfgpXE6+9Mo+yIwtMSjSI4sP/pNaywsb9Htk/paHf7ZmloMvm+b/lFvVGx9XiHC0bhg/uBaYcRLartTfzweEqIkWztHPRZ6oALtIIGCApQSMb7RGGp96A= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1765887738; c=relaxed/simple; bh=OK2GZo8+BBHN8L9u5k1ACdSJNL5tZ44SL9iC6QbG1Rk=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=qBPi15pKRp7Tvbcx/Av4f7UHHb7/QNAEMn/DbDUAUXl0A7zAncsaljvmPYbbLH0ZzsGjK5I8gffHAaxXznRgdNHzR049Sm+tQiznV85mXR1NqzsHpOXQBdr15VAl2OIzZWUv+cYp3qit25XJJ+n1LTVUH+rQKVaiJhmUXk7FwD0= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=linuxfoundation.org header.i=@linuxfoundation.org header.b=fV/YPnCS; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=linuxfoundation.org header.i=@linuxfoundation.org header.b="fV/YPnCS" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 0D9B2C4CEF1; Tue, 16 Dec 2025 12:22:17 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=linuxfoundation.org; s=korg; t=1765887738; bh=OK2GZo8+BBHN8L9u5k1ACdSJNL5tZ44SL9iC6QbG1Rk=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=fV/YPnCSE9eIc0igQWiwPaC8wKnDYY2rt9P26gpNa4UnRgcwQ1RqT//fJ7NOhr3Sg HqdZ08aZrNx2eTxg+w/6o8EZDNakWC5ydKXNLQCoHd6myQ6WSf3DxUpMdaWBMy36ej aCIvcsj7S6qXVs9emoVWp6CxMsjPwBZzlMtv12/A= From: Greg Kroah-Hartman To: stable@vger.kernel.org Cc: Greg Kroah-Hartman , patches@lists.linux.dev, Konrad Dybcio , Akhil P Oommen , Rob Clark , Sasha Levin Subject: [PATCH 6.18 323/614] drm/msm/a6xx: Fix the gemnoc workaround Date: Tue, 16 Dec 2025 12:11:30 +0100 Message-ID: <20251216111413.066560662@linuxfoundation.org> X-Mailer: git-send-email 2.52.0 In-Reply-To: <20251216111401.280873349@linuxfoundation.org> References: <20251216111401.280873349@linuxfoundation.org> User-Agent: quilt/0.69 X-stable: review X-Patchwork-Hint: ignore Precedence: bulk X-Mailing-List: patches@lists.linux.dev List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit 6.18-stable review patch. If anyone has any objections, please let me know. ------------------ From: Akhil P Oommen [ Upstream commit ff7a6de043fce21ea5891311746b16121b385c59 ] Correct the register offset and enable this workaround for all A7x and newer GPUs to match the recommendation. Also, downstream does this w/a after moving the fence to allow mode. So do the same. Fixes: dbfbb376b50c ("drm/msm/a6xx: Add A621 support") Reviewed-by: Konrad Dybcio Signed-off-by: Akhil P Oommen Patchwork: https://patchwork.freedesktop.org/patch/688997/ Message-ID: <20251118-kaana-gpu-support-v4-3-86eeb8e93fb6@oss.qualcomm.com> Signed-off-by: Rob Clark Signed-off-by: Sasha Levin --- drivers/gpu/drm/msm/adreno/a6xx_gmu.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gmu.c b/drivers/gpu/drm/msm/adreno/a6xx_gmu.c index 4e6dc16e4a4c4..605bb55de8d52 100644 --- a/drivers/gpu/drm/msm/adreno/a6xx_gmu.c +++ b/drivers/gpu/drm/msm/adreno/a6xx_gmu.c @@ -485,8 +485,9 @@ static void a6xx_gemnoc_workaround(struct a6xx_gmu *gmu) * in the power down sequence not being fully executed. That in turn can * prevent CX_GDSC from collapsing. Assert Qactive to avoid this. */ - if (adreno_is_a621(adreno_gpu) || adreno_is_7c3(adreno_gpu)) - gmu_write(gmu, REG_A6XX_GMU_AO_AHB_FENCE_CTRL, BIT(0)); + if (adreno_is_a7xx(adreno_gpu) || (adreno_is_a621(adreno_gpu) || + adreno_is_7c3(adreno_gpu))) + gmu_write(gmu, REG_A6XX_GPU_GMU_CX_GMU_CX_FALNEXT_INTF, BIT(0)); } /* Let the GMU know that we are about to go into slumber */ @@ -522,10 +523,9 @@ static int a6xx_gmu_notify_slumber(struct a6xx_gmu *gmu) } out: - a6xx_gemnoc_workaround(gmu); - /* Put fence into allow mode */ gmu_write(gmu, REG_A6XX_GMU_AO_AHB_FENCE_CTRL, 0); + a6xx_gemnoc_workaround(gmu); return ret; } -- 2.51.0