From: Daniel Mack <daniel@zonque.org>
To: linux-leds@vger.kernel.org
Cc: lee@kernel.org, Daniel Mack <daniel@zonque.org>
Subject: [PATCH v4 2/3] leds: is31f132xx: re-order code to remove forward declarations
Date: Fri, 19 Dec 2025 16:45:20 +0100 [thread overview]
Message-ID: <20251219154521.643312-3-daniel@zonque.org> (raw)
In-Reply-To: <20251219154521.643312-1-daniel@zonque.org>
Move the chipdef structs after the functions they reference so that forward
declarations become unnecessary.
Signed-off-by: Daniel Mack <daniel@zonque.org>
---
v2 -> v3: re-ordered patches to get rid of the forward declarations
before introducing more of them.
drivers/leds/leds-is31fl32xx.c | 128 ++++++++++++++++-----------------
1 file changed, 62 insertions(+), 66 deletions(-)
diff --git a/drivers/leds/leds-is31fl32xx.c b/drivers/leds/leds-is31fl32xx.c
index dc9349f9d350..bd5323f2316e 100644
--- a/drivers/leds/leds-is31fl32xx.c
+++ b/drivers/leds/leds-is31fl32xx.c
@@ -88,72 +88,6 @@ struct is31fl32xx_chipdef {
int (*sw_shutdown_func)(struct is31fl32xx_priv *priv, bool enable);
};
-static const struct is31fl32xx_chipdef is31fl3236_cdef = {
- .channels = 36,
- .shutdown_reg = 0x00,
- .pwm_update_reg = 0x25,
- .global_control_reg = 0x4a,
- .reset_reg = 0x4f,
- .output_frequency_setting_reg = IS31FL32XX_REG_NONE,
- .pwm_register_base = 0x01,
- .led_control_register_base = 0x26,
- .enable_bits_per_led_control_register = 1,
-};
-
-static const struct is31fl32xx_chipdef is31fl3236a_cdef = {
- .channels = 36,
- .shutdown_reg = 0x00,
- .pwm_update_reg = 0x25,
- .global_control_reg = 0x4a,
- .reset_reg = 0x4f,
- .output_frequency_setting_reg = 0x4b,
- .pwm_register_base = 0x01,
- .led_control_register_base = 0x26,
- .enable_bits_per_led_control_register = 1,
-};
-
-static const struct is31fl32xx_chipdef is31fl3235_cdef = {
- .channels = 28,
- .shutdown_reg = 0x00,
- .pwm_update_reg = 0x25,
- .global_control_reg = 0x4a,
- .reset_reg = 0x4f,
- .output_frequency_setting_reg = IS31FL32XX_REG_NONE,
- .pwm_register_base = 0x05,
- .led_control_register_base = 0x2a,
- .enable_bits_per_led_control_register = 1,
-};
-
-static const struct is31fl32xx_chipdef is31fl3218_cdef = {
- .channels = 18,
- .shutdown_reg = 0x00,
- .pwm_update_reg = 0x16,
- .global_control_reg = IS31FL32XX_REG_NONE,
- .reset_reg = 0x17,
- .output_frequency_setting_reg = IS31FL32XX_REG_NONE,
- .pwm_register_base = 0x01,
- .led_control_register_base = 0x13,
- .enable_bits_per_led_control_register = 6,
-};
-
-static int is31fl3216_reset(struct is31fl32xx_priv *priv);
-static int is31fl3216_software_shutdown(struct is31fl32xx_priv *priv,
- bool enable);
-static const struct is31fl32xx_chipdef is31fl3216_cdef = {
- .channels = 16,
- .shutdown_reg = IS31FL32XX_REG_NONE,
- .pwm_update_reg = 0xB0,
- .global_control_reg = IS31FL32XX_REG_NONE,
- .reset_reg = IS31FL32XX_REG_NONE,
- .output_frequency_setting_reg = IS31FL32XX_REG_NONE,
- .pwm_register_base = 0x10,
- .pwm_registers_reversed = true,
- .led_control_register_base = 0x01,
- .enable_bits_per_led_control_register = 8,
- .reset_func = is31fl3216_reset,
- .sw_shutdown_func = is31fl3216_software_shutdown,
-};
-
static int is31fl32xx_write(struct is31fl32xx_priv *priv, u8 reg, u8 val)
{
int ret;
@@ -435,6 +369,68 @@ static int is31fl32xx_parse_dt(struct device *dev,
return 0;
}
+static const struct is31fl32xx_chipdef is31fl3236_cdef = {
+ .channels = 36,
+ .shutdown_reg = 0x00,
+ .pwm_update_reg = 0x25,
+ .global_control_reg = 0x4a,
+ .reset_reg = 0x4f,
+ .output_frequency_setting_reg = IS31FL32XX_REG_NONE,
+ .pwm_register_base = 0x01,
+ .led_control_register_base = 0x26,
+ .enable_bits_per_led_control_register = 1,
+};
+
+static const struct is31fl32xx_chipdef is31fl3236a_cdef = {
+ .channels = 36,
+ .shutdown_reg = 0x00,
+ .pwm_update_reg = 0x25,
+ .global_control_reg = 0x4a,
+ .reset_reg = 0x4f,
+ .output_frequency_setting_reg = 0x4b,
+ .pwm_register_base = 0x01,
+ .led_control_register_base = 0x26,
+ .enable_bits_per_led_control_register = 1,
+};
+
+static const struct is31fl32xx_chipdef is31fl3235_cdef = {
+ .channels = 28,
+ .shutdown_reg = 0x00,
+ .pwm_update_reg = 0x25,
+ .global_control_reg = 0x4a,
+ .reset_reg = 0x4f,
+ .output_frequency_setting_reg = IS31FL32XX_REG_NONE,
+ .pwm_register_base = 0x05,
+ .led_control_register_base = 0x2a,
+ .enable_bits_per_led_control_register = 1,
+};
+
+static const struct is31fl32xx_chipdef is31fl3218_cdef = {
+ .channels = 18,
+ .shutdown_reg = 0x00,
+ .pwm_update_reg = 0x16,
+ .global_control_reg = IS31FL32XX_REG_NONE,
+ .reset_reg = 0x17,
+ .output_frequency_setting_reg = IS31FL32XX_REG_NONE,
+ .pwm_register_base = 0x01,
+ .led_control_register_base = 0x13,
+ .enable_bits_per_led_control_register = 6,
+};
+
+static const struct is31fl32xx_chipdef is31fl3216_cdef = {
+ .channels = 16,
+ .shutdown_reg = IS31FL32XX_REG_NONE,
+ .pwm_update_reg = 0xB0,
+ .global_control_reg = IS31FL32XX_REG_NONE,
+ .reset_reg = IS31FL32XX_REG_NONE,
+ .output_frequency_setting_reg = IS31FL32XX_REG_NONE,
+ .pwm_register_base = 0x10,
+ .pwm_registers_reversed = true,
+ .led_control_register_base = 0x01,
+ .enable_bits_per_led_control_register = 8,
+ .reset_func = is31fl3216_reset,
+ .sw_shutdown_func = is31fl3216_software_shutdown,
+};
static const struct of_device_id of_is31fl32xx_match[] = {
{ .compatible = "issi,is31fl3236", .data = &is31fl3236_cdef, },
--
2.52.0
next prev parent reply other threads:[~2025-12-19 15:45 UTC|newest]
Thread overview: 5+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-12-19 15:45 [PATCH v4 0/3] leds: is31f132xx: add support for is31fl3293 Daniel Mack
2025-12-19 15:45 ` [PATCH v4 1/3] dt-bindings: leds: add issi,is31fl3293 to leds-is31fl32xx Daniel Mack
2025-12-19 15:45 ` Daniel Mack [this message]
2025-12-19 15:45 ` [PATCH v4 3/3] leds: is31f132xx: add support for is31fl3293 Daniel Mack
2026-01-09 11:27 ` [PATCH v4 0/3] " Lee Jones
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