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X-CSE-ConnectionGUID: +obQgw5bTGCE6Kg9EviJqQ== X-CSE-MsgGUID: rL6lC3xzStGpZtBGqmRAuA== X-IronPort-AV: E=McAfee;i="6800,10657,11649"; a="68100817" X-IronPort-AV: E=Sophos;i="6.21,166,1763452800"; d="scan'208";a="68100817" Received: from fmviesa008.fm.intel.com ([10.60.135.148]) by orvoesa111.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 21 Dec 2025 06:36:02 -0800 X-CSE-ConnectionGUID: yVYNb4CTRhizKXRmTPbPyw== X-CSE-MsgGUID: aFWaeblxTUmUjSfVF38IrQ== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.21,166,1763452800"; d="scan'208";a="199611111" Received: from igk-lkp-server01.igk.intel.com (HELO 8a0c053bdd2a) ([10.211.93.152]) by fmviesa008.fm.intel.com with ESMTP; 21 Dec 2025 06:36:01 -0800 Received: from kbuild by 8a0c053bdd2a with local (Exim 4.98.2) (envelope-from ) id 1vXKXO-0000000054y-3crL; Sun, 21 Dec 2025 14:35:58 +0000 Date: Sun, 21 Dec 2025 15:35:44 +0100 From: kernel test robot To: oe-kbuild@lists.linux.dev Cc: lkp@intel.com Subject: Re: [PATCH v3 5/6] riscv: dts: anlogic: add clocks and CRU for DR1V90 Message-ID: <202512211545.fkHSicDM-lkp@intel.com> Precedence: bulk X-Mailing-List: oe-kbuild@lists.linux.dev List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline :::::: :::::: Manual check reason: "dtcheck: binding changes may go via different trees" :::::: BCC: lkp@intel.com CC: oe-kbuild-all@lists.linux.dev In-Reply-To: <20251216-dr1v90-cru-v3-5-52cc938d1db0@pigmoral.tech> References: <20251216-dr1v90-cru-v3-5-52cc938d1db0@pigmoral.tech> TO: Junhui Liu TO: Michael Turquette TO: Stephen Boyd TO: Rob Herring TO: Krzysztof Kozlowski TO: Conor Dooley TO: Philipp Zabel TO: Junhui Liu TO: Paul Walmsley TO: Palmer Dabbelt TO: Albert Ou TO: Alexandre Ghiti CC: linux-clk@vger.kernel.org CC: linux-kernel@vger.kernel.org CC: linux-riscv@lists.infradead.org CC: devicetree@vger.kernel.org Hi Junhui, kernel test robot noticed the following build warnings: [auto build test WARNING on 8f0b4cce4481fb22653697cced8d0d04027cb1e8] url: https://github.com/intel-lab-lkp/linux/commits/Junhui-Liu/clk-correct-clk_div_mask-return-value-for-width-32/20251216-115101 base: 8f0b4cce4481fb22653697cced8d0d04027cb1e8 patch link: https://lore.kernel.org/r/20251216-dr1v90-cru-v3-5-52cc938d1db0%40pigmoral.tech patch subject: [PATCH v3 5/6] riscv: dts: anlogic: add clocks and CRU for DR1V90 :::::: branch date: 5 days ago :::::: commit date: 5 days ago config: riscv-randconfig-2051-20251217 (https://download.01.org/0day-ci/archive/20251221/202512211545.fkHSicDM-lkp@intel.com/config) compiler: riscv64-linux-gcc (GCC) 15.1.0 dtschema version: 2025.12 reproduce (this is a W=1 build): (https://download.01.org/0day-ci/archive/20251221/202512211545.fkHSicDM-lkp@intel.com/reproduce) If you fix the issue in a separate patch/commit (i.e. not just a new version of the same patch/commit), kindly add following tags | Reported-by: kernel test robot | Closes: https://lore.kernel.org/r/202512211545.fkHSicDM-lkp@intel.com/ dtcheck warnings: (new ones prefixed by >>) >> arch/riscv/boot/dts/anlogic/dr1v90-mlkpai-fs01.dtb: clock-ext-can (fixed-clock): 'clock-frequency' is a required property from schema $id: http://devicetree.org/schemas/clock/fixed-clock.yaml >> arch/riscv/boot/dts/anlogic/dr1v90-mlkpai-fs01.dtb: clock-ext-wdt (fixed-clock): 'clock-frequency' is a required property from schema $id: http://devicetree.org/schemas/clock/fixed-clock.yaml -- 0-DAY CI Kernel Test Service https://github.com/intel/lkp-tests/wiki