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envelope-from=deller@kernel.org; helo=tor.source.kernel.org X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org From: Soumyajyotii Ssarkar These fixes ensure proper interrupt signaling and status register behavior during SCSI operations: - Mask DFE bit in ncr710_update_irq() - Remove manual ISTAT_DIP clearing, let ncr710_update_irq() handle it consistently - Fix SSTAT0 read to clear unconditionally when non zero - Fix SSTAT2 read was returning DSTAT instead - Preserve DFE status bit when clearing DSTAT Signed-off-by: Soumyajyotii Ssarkar Tested-by: Helge Deller Signed-off-by: Helge Deller --- hw/scsi/ncr53c710.c | 15 +++------------ 1 file changed, 3 insertions(+), 12 deletions(-) diff --git a/hw/scsi/ncr53c710.c b/hw/scsi/ncr53c710.c index ac1ca4cef8..0b7734a129 100644 --- a/hw/scsi/ncr53c710.c +++ b/hw/scsi/ncr53c710.c @@ -593,7 +593,7 @@ static void ncr710_update_irq(NCR710State *s) { int level = 0; - if (s->dstat) { + if (s->dstat & ~NCR710_DSTAT_DFE) { if (s->dstat & s->dien) { level = 1; } @@ -1785,7 +1785,6 @@ static uint8_t ncr710_reg_readb(NCR710State *s, int offset) } s->dstat = 0; /* Clear all DMA interrupt status bits */ s->dstat |= NCR710_DSTAT_DFE; - s->istat &= ~NCR710_ISTAT_DIP; ncr710_update_irq(s); if (s->waiting == NCR710_WAIT_RESELECT && s->current && @@ -1811,7 +1810,7 @@ static uint8_t ncr710_reg_readb(NCR710State *s, int offset) return ret; case NCR710_SSTAT0_REG: /* SSTAT0 */ ret = s->sstat0; - if (s->sstat0 != 0 && !(s->sstat0 & NCR710_SSTAT0_STO)) { + if (s->sstat0 != 0) { s->sstat0 = 0; s->istat &= ~NCR710_ISTAT_SIP; ncr710_update_irq(s); @@ -1824,14 +1823,7 @@ static uint8_t ncr710_reg_readb(NCR710State *s, int offset) ret = s->sstat0; break; case NCR710_SSTAT2_REG: /* SSTAT2 */ - ret = s->dstat; - - if (s->dstat & NCR710_DSTAT_SIR) { - /* SIR bit processing */ - } - s->dstat = 0; - s->istat &= ~NCR710_ISTAT_DIP; - ncr710_update_irq(s); + ret = s->sstat2; break; CASE_GET_REG32(dsa, NCR710_DSA_REG) break; @@ -1902,7 +1894,6 @@ static uint8_t ncr710_reg_readb(NCR710State *s, int offset) if (s->dsps == GOOD_STATUS_AFTER_STATUS && (s->dstat & NCR710_DSTAT_SIR)) { s->dstat &= ~NCR710_DSTAT_SIR; - s->istat &= ~NCR710_ISTAT_DIP; ncr710_update_irq(s); } break; -- 2.52.0