From: George Guo <dongtai.guo@linux.dev>
To: hengqi.chen@gmail.com
Cc: chenhuacai@kernel.org, dongtai.guo@linux.dev,
guodongtai@kylinos.cn, kernel@xen0n.name,
lianyangyang@kylinos.cn, linux-kernel@vger.kernel.org,
loongarch@lists.linux.dev, r@hev.cc, xry111@xry111.site
Subject: [PATCH v8 loongarch-next 1/3] LoongArch: Add SCQ support detection
Date: Wed, 31 Dec 2025 11:45:21 +0800 [thread overview]
Message-ID: <20251231034523.47014-2-dongtai.guo@linux.dev> (raw)
In-Reply-To: <20251231034523.47014-1-dongtai.guo@linux.dev>
From: George Guo <guodongtai@kylinos.cn>
Check CPUCFG2_SCQ bit to determine if the CPU supports
SCQ instruction.
Co-developed-by: Yangyang Lian <lianyangyang@kylinos.cn>
Signed-off-by: Yangyang Lian <lianyangyang@kylinos.cn>
Signed-off-by: George Guo <guodongtai@kylinos.cn>
---
arch/loongarch/include/asm/cpu-features.h | 1 +
arch/loongarch/include/asm/cpu.h | 2 ++
arch/loongarch/include/asm/loongarch.h | 1 +
arch/loongarch/kernel/cpu-probe.c | 2 ++
arch/loongarch/kernel/proc.c | 1 +
5 files changed, 7 insertions(+)
diff --git a/arch/loongarch/include/asm/cpu-features.h b/arch/loongarch/include/asm/cpu-features.h
index 3745d991a99a..39c7fe64c3ef 100644
--- a/arch/loongarch/include/asm/cpu-features.h
+++ b/arch/loongarch/include/asm/cpu-features.h
@@ -67,5 +67,6 @@
#define cpu_has_msgint cpu_opt(LOONGARCH_CPU_MSGINT)
#define cpu_has_avecint cpu_opt(LOONGARCH_CPU_AVECINT)
#define cpu_has_redirectint cpu_opt(LOONGARCH_CPU_REDIRECTINT)
+#define cpu_has_scq cpu_opt(LOONGARCH_CPU_SCQ)
#endif /* __ASM_CPU_FEATURES_H */
diff --git a/arch/loongarch/include/asm/cpu.h b/arch/loongarch/include/asm/cpu.h
index f3efb00b6141..5531039027ec 100644
--- a/arch/loongarch/include/asm/cpu.h
+++ b/arch/loongarch/include/asm/cpu.h
@@ -125,6 +125,7 @@ static inline char *id_to_core_name(unsigned int id)
#define CPU_FEATURE_MSGINT 29 /* CPU has MSG interrupt */
#define CPU_FEATURE_AVECINT 30 /* CPU has AVEC interrupt */
#define CPU_FEATURE_REDIRECTINT 31 /* CPU has interrupt remapping */
+#define CPU_FEATURE_SCQ 32 /* CPU has SC.Q instruction */
#define LOONGARCH_CPU_CPUCFG BIT_ULL(CPU_FEATURE_CPUCFG)
#define LOONGARCH_CPU_LAM BIT_ULL(CPU_FEATURE_LAM)
@@ -158,5 +159,6 @@ static inline char *id_to_core_name(unsigned int id)
#define LOONGARCH_CPU_MSGINT BIT_ULL(CPU_FEATURE_MSGINT)
#define LOONGARCH_CPU_AVECINT BIT_ULL(CPU_FEATURE_AVECINT)
#define LOONGARCH_CPU_REDIRECTINT BIT_ULL(CPU_FEATURE_REDIRECTINT)
+#define LOONGARCH_CPU_SCQ BIT_ULL(CPU_FEATURE_SCQ)
#endif /* _ASM_CPU_H */
diff --git a/arch/loongarch/include/asm/loongarch.h b/arch/loongarch/include/asm/loongarch.h
index e6b8ff61c8cc..817cd90941d9 100644
--- a/arch/loongarch/include/asm/loongarch.h
+++ b/arch/loongarch/include/asm/loongarch.h
@@ -94,6 +94,7 @@
#define CPUCFG2_LSPW BIT(21)
#define CPUCFG2_LAM BIT(22)
#define CPUCFG2_PTW BIT(24)
+#define CPUCFG2_SCQ BIT(30)
#define LOONGARCH_CPUCFG3 0x3
#define CPUCFG3_CCDMA BIT(0)
diff --git a/arch/loongarch/kernel/cpu-probe.c b/arch/loongarch/kernel/cpu-probe.c
index 08a227034042..382c472c6bfe 100644
--- a/arch/loongarch/kernel/cpu-probe.c
+++ b/arch/loongarch/kernel/cpu-probe.c
@@ -205,6 +205,8 @@ static void cpu_probe_common(struct cpuinfo_loongarch *c)
c->options |= LOONGARCH_CPU_PTW;
elf_hwcap |= HWCAP_LOONGARCH_PTW;
}
+ if (config & CPUCFG2_SCQ)
+ c->options |= LOONGARCH_CPU_SCQ;
if (config & CPUCFG2_LSPW) {
c->options |= LOONGARCH_CPU_LSPW;
elf_hwcap |= HWCAP_LOONGARCH_LSPW;
diff --git a/arch/loongarch/kernel/proc.c b/arch/loongarch/kernel/proc.c
index a8800d20e11b..252fa1d03b85 100644
--- a/arch/loongarch/kernel/proc.c
+++ b/arch/loongarch/kernel/proc.c
@@ -75,6 +75,7 @@ static int show_cpuinfo(struct seq_file *m, void *v)
if (cpu_has_lbt_x86) seq_printf(m, " lbt_x86");
if (cpu_has_lbt_arm) seq_printf(m, " lbt_arm");
if (cpu_has_lbt_mips) seq_printf(m, " lbt_mips");
+ if (cpu_has_scq) seq_printf(m, " scq");
seq_printf(m, "\n");
seq_printf(m, "Hardware Watchpoint\t: %s", str_yes_no(cpu_has_watch));
--
2.49.0
next prev parent reply other threads:[~2025-12-31 3:45 UTC|newest]
Thread overview: 30+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-12-15 8:11 [PATCH v6 0/4] LoongArch: Add 128-bit atomic cmpxchg support (v5) George Guo
2025-12-15 8:11 ` [PATCH v6 1/4] LoongArch: Add SCQ support detection George Guo
2025-12-15 8:11 ` [PATCH v6 2/4] LoongArch: Add 128-bit atomic cmpxchg support George Guo
2025-12-15 8:11 ` [PATCH v6 3/4] LoongArch: Use spinlock to emulate 128-bit cmpxchg George Guo
2025-12-20 13:41 ` [PATCH v6 0/4] LoongArch: Add 128-bit atomic cmpxchg support (v5) Hengqi Chen
2025-12-29 6:34 ` [PATCH loongarch-next 0/4] LoongArch: Add 128-bit atomic cmpxchg support George Guo
2025-12-29 6:34 ` [PATCH loongarch-next 1/4] LoongArch: Add SCQ support detection George Guo
2025-12-29 6:34 ` [PATCH loongarch-next 2/4] LoongArch: Add 128-bit atomic cmpxchg support George Guo
2025-12-29 6:34 ` [PATCH loongarch-next 3/4] LoongArch: Use spinlock to emulate 128-bit cmpxchg George Guo
2025-12-29 6:34 ` [PATCH loongarch-next 4/4] LoongArch: Enable 128-bit atomics cmpxchg support George Guo
2025-12-29 14:21 ` [PATCH loongarch-next 0/4] LoongArch: Add 128-bit atomic " Hengqi Chen
2025-12-30 1:34 ` [PATCH v7 " George Guo
2025-12-30 1:34 ` [PATCH v7 loongarch-next 1/4] LoongArch: Add SCQ support detection George Guo
2025-12-30 12:05 ` Hengqi Chen
2025-12-30 12:07 ` Hengqi Chen
2025-12-30 1:34 ` [PATCH v7 loongarch-next 2/4] LoongArch: Add 128-bit atomic cmpxchg support George Guo
2025-12-30 12:17 ` Hengqi Chen
2025-12-30 1:34 ` [PATCH v7 loongarch-next 3/4] LoongArch: Use spinlock to emulate 128-bit cmpxchg George Guo
2025-12-30 1:34 ` [PATCH v7 loongarch-next 4/4] LoongArch: Enable 128-bit atomics cmpxchg support George Guo
2025-12-30 12:19 ` Hengqi Chen
2025-12-30 12:04 ` [PATCH v7 loongarch-next 0/4] LoongArch: Add 128-bit atomic " Hengqi Chen
2025-12-31 3:45 ` [PATCH v8 loongarch-next 0/3] " George Guo
2025-12-31 3:45 ` George Guo [this message]
2025-12-31 9:51 ` [PATCH v8 loongarch-next 1/3] LoongArch: Add SCQ support detection Hengqi Chen
2025-12-31 3:45 ` [PATCH v8 loongarch-next 2/3] LoongArch: Add 128-bit atomic cmpxchg support George Guo
2025-12-31 9:53 ` Hengqi Chen
2025-12-31 3:45 ` [PATCH v8 loongarch-next 3/3] LoongArch: Enable 128-bit atomics " George Guo
2025-12-31 9:52 ` Hengqi Chen
2025-12-31 9:56 ` [PATCH v8 loongarch-next 0/3] LoongArch: Add 128-bit atomic " Huacai Chen
2025-12-20 13:55 ` [PATCH v6 0/4] LoongArch: Add 128-bit atomic cmpxchg support (v5) Hengqi Chen
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