[PATCH v3 2/2] arm: add DCZID_EL0 to idregs array

[Cornelia Huck <cohuck@redhat.com>]

Continue moving ID registers to the idregs array, so that we
eventually can switch to an autogenerated cpu-sysregs.h.inc.

This requires a bit of care, since we still have to handle the EL
specific part (DCZID_EL0.DZP). The value previously saved in
cpu->dcz_blocksize is now kept in DCZID_EL.BS (transparent to
callers using the wrappers.)

KVM currently does not support DCZID_EL0 via ONE_REG, assert that
we're not trying to do anything with it until it does.

Signed-off-by: Cornelia Huck <cohuck@redhat.com>
---
 target/arm/cpu-sysregs.h.inc | 1 +
 target/arm/cpu.h             | 8 ++++----
 target/arm/helper.c          | 4 +++-
 target/arm/tcg/translate.h   | 2 +-
 4 files changed, 9 insertions(+), 6 deletions(-)

diff --git a/target/arm/cpu-sysregs.h.inc b/target/arm/cpu-sysregs.h.inc
index 2bb2861c6234..7f3aa8b991aa 100644
--- a/target/arm/cpu-sysregs.h.inc
+++ b/target/arm/cpu-sysregs.h.inc
@@ -39,3 +39,4 @@ DEF(ID_MMFR5_EL1, 3, 0, 0, 3, 6)
 DEF(CLIDR_EL1, 3, 1, 0, 0, 1)
 DEF(ID_AA64ZFR0_EL1, 3, 0, 0, 4, 4)
 DEF(CTR_EL0, 3, 3, 0, 0, 1)
+DEF(DCZID_EL0, 3, 3, 0, 0, 7)
diff --git a/target/arm/cpu.h b/target/arm/cpu.h
index c0dae1a891a7..08b7d3fb936a 100644
--- a/target/arm/cpu.h
+++ b/target/arm/cpu.h
@@ -1111,8 +1111,6 @@ struct ArchCPU {
     bool prop_pauth_qarma5;
     bool prop_lpa2;
 
-    /* DCZ blocksize, in log_2(words), ie low 4 bits of DCZID_EL0 */
-    uint8_t dcz_blocksize;
     /* GM blocksize, in log_2(words), ie low 4 bits of GMID_EL0 */
     uint8_t gm_blocksize;
 
@@ -1180,12 +1178,14 @@ struct ARMCPUClass {
 
 static inline uint8_t get_dczid_bs(ARMCPU *cpu)
 {
-    return cpu->dcz_blocksize;
+    return extract64(cpu->isar.idregs[DCZID_EL0_IDX], 0, 4);
 }
 
 static inline void set_dczid_bs(ARMCPU *cpu, uint8_t bs)
 {
-    cpu->dcz_blocksize = bs;
+    /* keep dzp unchanged */
+    cpu->isar.idregs[DCZID_EL0_IDX] =
+        deposit64(cpu->isar.idregs[DCZID_EL0_IDX], 0, 4, bs);
 }
 
 /* Callback functions for the generic timer's timers. */
diff --git a/target/arm/helper.c b/target/arm/helper.c
index 61b3b90b63c0..2bcb01e45bbf 100644
--- a/target/arm/helper.c
+++ b/target/arm/helper.c
@@ -3320,12 +3320,14 @@ static uint64_t aa64_dczid_read(CPUARMState *env, const ARMCPRegInfo *ri)
     ARMCPU *cpu = env_archcpu(env);
     int dzp_bit = 1 << 4;
 
+    assert(!kvm_enabled());
+
     /* DZP indicates whether DC ZVA access is allowed */
     if (aa64_zva_access(env, NULL, false) == CP_ACCESS_OK) {
         dzp_bit = 0;
     }
 
-    return cpu->dcz_blocksize | dzp_bit;
+    return cpu->isar.idregs[DCZID_EL0_IDX] | dzp_bit;
 }
 
 static CPAccessResult sp_el0_access(CPUARMState *env, const ARMCPRegInfo *ri,
diff --git a/target/arm/tcg/translate.h b/target/arm/tcg/translate.h
index b62104b4ae88..1e30d7c77c37 100644
--- a/target/arm/tcg/translate.h
+++ b/target/arm/tcg/translate.h
@@ -193,7 +193,7 @@ typedef struct DisasContext {
      *  < 0, set by the current instruction.
      */
     int8_t btype;
-    /* A copy of cpu->dcz_blocksize. */
+    /* A copy of DCZID_EL0.BS. */
     uint8_t dcz_blocksize;
     /* A copy of cpu->gm_blocksize. */
     uint8_t gm_blocksize;
-- 
2.52.0