From: Mika Westerberg <mika.westerberg@linux.intel.com>
To: Mario Limonciello <superm1@kernel.org>
Cc: "open list:THUNDERBOLT DRIVER" <linux-usb@vger.kernel.org>,
linux-kernel@vger.kernel.org,
Andreas Noever <andreas.noever@gmail.com>,
Michael Jamet <michael.jamet@intel.com>,
Yehezkel Bernat <YehezkelShB@gmail.com>
Subject: Re: [PATCH v2 0/2] thunderbolt: Fix S4 resume incongruities
Date: Thu, 8 Jan 2026 12:42:05 +0100 [thread overview]
Message-ID: <20260108114205.GS2275908@black.igk.intel.com> (raw)
In-Reply-To: <158442b3-28c2-4f8c-ba42-0b9c6661c650@kernel.org>
On Wed, Jan 07, 2026 at 02:50:54PM -0600, Mario Limonciello wrote:
> On 1/7/26 3:33 AM, Mika Westerberg wrote:
> > Hi,
> >
> > On Mon, Jan 05, 2026 at 11:37:47PM -0600, Mario Limonciello (AMD) wrote:
> > > When a machine is restored from S4 if the firmware CM has created
> > > tunnels there can be an incongruity of expectation from the kernel
> > > when compared to booting from S5. This series addresses those.
> >
> > I suspect there is no Firmware CM in AMD platforms so this actually means
> > the BIOS CM, correct?
>
> That's correct.
>
> >
> > However, on S4 we actually do reset host router when the "boot kernel" is
> > started before loading and jumping to the hibernation image.
>
> That's only if thunderbolt.ko is built into the kernel or is included in the
> initramfs before it does the pivot to the hibernation image.
Ah good point.
> At least in the tests we were doing it's not part of the boot kernel.
>
> > It might be
> > that this boot kernel tunnel configuration is causing the issues you are
> > seeing (can you elaborate on those?)
>
> The issues manifest "downstream" in the GPU driver. There are a bunch of
> aux failures and a non functional display. Tracing it back the GPU driver
> isn't alive at the time that the tunnels are attempted to be reconstructed
> at the moment and so CM tears DP tunnel down and then when GPU driver does
> come up it is not functional.
>
> DP tunnel constructed at:
>
> [ 486.007194] thunderbolt 0000:c6:00.6: AUX RX path activation complete
>
> First DPRx timeout at:
>
> [ 486.135483] thunderbolt 0000:c6:00.6: 0:6 <-> 2:13 (DP): DPRX read
> timeout
>
> DP tunnel deactivating at:
>
> [ 486.331856] thunderbolt 0000:c6:00.6: 0:6 <-> 2:13 (DP): deactivating
Hmm, we have dprx_timeout by default 12 seconds. How come it tears down the
tunnel already?
>
> First DPRx DPCD reading starts at:
>
> [ 486.351765] amdgpu 0000:c4:00.0: amdgpu: [drm] DPIA AUX failed on
> 0xf0000(10), error 7
This would have maked it within the 12s if I read the timestamps right.
next prev parent reply other threads:[~2026-01-08 11:42 UTC|newest]
Thread overview: 19+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-01-06 5:37 [PATCH v2 0/2] thunderbolt: Fix S4 resume incongruities Mario Limonciello (AMD)
2026-01-06 5:37 ` [PATCH v2 1/2] thunderbolt: Move nhi_reset before pmops declaration Mario Limonciello (AMD)
2026-01-06 5:37 ` [PATCH v2 2/2] thunderbolt: Reset NHI during S4 restore_noirq() callback Mario Limonciello (AMD)
2026-01-07 9:33 ` [PATCH v2 0/2] thunderbolt: Fix S4 resume incongruities Mika Westerberg
2026-01-07 20:50 ` Mario Limonciello
2026-01-08 11:42 ` Mika Westerberg [this message]
2026-01-08 19:18 ` Mario Limonciello
2026-01-09 7:23 ` Mika Westerberg
2026-01-09 15:38 ` Mario Limonciello
2026-01-10 0:42 ` Katiyar, Pooja
2026-01-13 18:44 ` Mario Limonciello (AMD) (kernel.org)
2026-01-17 16:57 ` Katiyar, Pooja
2026-01-19 19:59 ` Mario Limonciello (AMD) (kernel.org)
2026-01-19 22:13 ` Kenneth Crudup
2026-01-29 23:13 ` Katiyar, Pooja
2026-01-30 1:39 ` Kenneth Crudup
2026-01-30 1:42 ` Kenneth Crudup
2026-02-04 0:50 ` Katiyar, Pooja
2026-05-05 21:21 ` Mario Limonciello
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